SST49LF016C datasheet(29/43 Pages) MICROCHIP

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DS20005029B

02/16

16 Mbit LPC Serial Flash

SST49LF016C

EOL Data Sheet

AAI Data Load Protocol

Figure 9: AAI Load Protocol Waveform

Table 19: AAI Programming Cycle (initiated with WP#/AAI at VH ONLY)

Clock

Cycle

Field Name Field Contents LAD[3:0]

Comments

START

1110

LFRAME# must be active (low) for the part to respond.

Only the last start field (before LFRAME# transitions

high) should be recognized. The START field contents

indicate a Firmware Memory Write cycle. (1110b)

IDSEL

0000b to 1111b IN

ID works identically to Firmware Memory cycle.

This field indicates which SST49LF016C device

should respond. If the IDSEL (ID select) field matches

the value of ID[3:0], then that particular device will

respond to the whole bus cycle.

3-9

MADDR

YYYY

These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

Only bits [20:7] of the total address [27:0] are used for

AAI mode. The rest are “don’t care”.

MSIZE

KKKK

MSIZE field is don’t care when in AAI mode

11-266

DATA

ZZZZ

Data is transmitted to the device least significant nib-

ble first, from byte 0 to byte 127 as long as the RY/BY#

is high and LD# low. The host will pause the clock and

data stream when RY/BY# goes low until it returns

high, signifying that the chip is ready for more data

T19.0 20005029

1 2 3 4 5 6 7 8 9 10 11 12

266

264

WP#/AAI

LAD[3:0]

LCLK

(Data Strobe Input)

LD#

LFRAME#

RY/BY#

Start

IDSEL

MSIZE

MADDR

Address

Byte 0

Byte N

Byte

N+1

Byte

126

Byte

127

DATA

DATA DATA

1237 F08.1

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