SST49LF016C datasheet(15/43 Pages) MICROCHIP

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DS20005029B

02/16

16 Mbit LPC Serial Flash

SST49LF016C

EOL Data Sheet

Non-boundary-aligned address:

The SST49LF016C accepts multi-byte transfers for both Read and Write operations. The device

address space is divided into uniform page sizes 2, 4, 16, or 128 bytes wide, according to the MSIZE

value (see Table 6). The host issues only one address in the MADDR field of the Firmware Memory

Cycle, but multiple bytes are read from or written to the device. For this reason the MADDR address

should be page boundary-aligned. This means the address should be aligned to a Word boundary (A0

= 0) for a 2-byte transfer, a double Word boundary (e.g. A0 = 0, A1 = 0) for a 4-byte transfer, and so on.

If the address supplied by the host is not page boundary-aligned, the SST49LF016C will force a

boundary alignment, starting the multi-byte Read or Write operation from the lower byte of the

addressed page.

Multiple Device Selection

Multiple LPC serial flash devices may be strapped to increase memory densities in a system. The four

ID pins, ID[3:0], allow up to 16 devices to be attached to the same bus by using different ID strapping in

a system. BIOS support, bus loading, or the attaching bridge may limit this number. The boot device

must have an ID of 0000b (determined by ID[3:0]); subsequent devices use incremental numbering.

Equal density must be used with multiple devices.

Multiple Device Selection for Firmware Memory Cycle

For Firmware Memory Read/Write cycles, hardware strapping values on ID[3:0] must match the values

in IDSEL field. The SST49LF016C will compare these bits with ID[3:0]’s strapping values. If there is a

mismatch, the device will ignore the remainder of the cycle. See Table 7 for Multiple Device Selection

Configuration.

Table 7: Firmware Memory Multiple Device Selection Configuration

Device #

ID[3:0]

IDSEL

0 (Boot device)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

T7.0 20005029

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