HT46R23 datasheet(8/42 Pages) HOLTEK

8 / 42 page

HT46R23

Rev. 1.30

August 17, 2001

Stack register - STACK

This is a special part of the memory which is used to

save the contents of the program counter (PC) only. The

stack is organized into 8 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writeable. The activated level is indexed by the

stack pointer (SP) and is neither readable nor writeable.

At a subroutine call or interrupt acknowledgment, the

contents of the program counter are pushed onto the

stack. At the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI), the pro-

gram counter is restored to its previous value from the

stack. After a chip reset, the SP will point to the top of the

stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledgment will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a ²CALL² is sub-

sequently executed, stack overflow occurs and the first

entry will be lost (only the most recent 8 return ad-

dresses are stored).

Data memory - RAM

The data memory is designed with 224´8 bits. The

data memory is divided into two functional groups: spe-

cial function registers and general purpose data mem-

ory (192´8). Most are read/write, but some are read

only.

The special function registers include the indirect ad-

dressing registers (00H;02H), timer/event counter

higher-order byte register (TMRH;0CH), timer/event

counter low-order byte register (TMRL;0DH),

timer/event counter control register (TMRC;0EH), pro-

gram counter lower-order byte register (PCL;06H),

memory pointer registers (MP0;01H, MP1;03H), accu-

mulator (ACC;05H), table pointer (TBLP;07H), table

higher-order byte register (TBLH;08H), status register

(STATUS;0AH), interrupt control register (INTC0;

0BH), PWM data register (PWM0;1AH, PWM1;1BH),

the I2C BUS slave address register (HADR;20H), the I2C

BUS control register (HCR;21H), the I2C BUS status regis-

ter (HSR;22H), the I2C BUS data register (HDR;23H), the

A/D result lower-order byte register (ADRL;24H), the A/D

result higher-order byte register (ADRH;25H), the A/D con-

trol register (ADCR;26H), the A/D clock setting register

(ACSR;27H), I/O registers (PA;12H, PB;14H, PC;16H,

PD;18H) and I/O control registers (PAC;13H, PBC;15H,

PCC;17H, PDC;19H). The remaining space before the

40H is reserved for future expanded usage and reading

these locations will get ²00H². The general purpose data

memory, addressed from 40H to FFH, is used for data

and control information under instruction commands.

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by ²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer registers (MP0;01H/MP1;03H).

S peci a l P u r pos e

DA T A M E M O R Y

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0A H

0B H

0C H

0D H

0E H

0F H

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1A H

1B H

1C H

1D H

1E H

1F H

: U n u s e d

R ead a s " 00"

G ene r a l P u r p os e

DA T A M E M O R Y

( 192 B y t e s )

FF H

40H

20 H

21 H

22 H

23 H

24 H

25 H

26 H

27 H

28 H

3F H

I ndi r e ct A ddr es s i ng R egi s t er 0

MP 0

I ndi r e ct A ddr es s i ng R egi s t er 1

MP 1

AC C

PC L

TB L P

TB L H

ST AT U S

IN T C 0

TM R H

TM R L

TM R C

PA C

PB C

PC C

PD C

PW M 0

PW M 1

IN T C 1

HA DR

HCR

HS R

HDR

AD R L

AD R H

AD C R

AC SR

RAM mapping

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