HT46R23 datasheet(17/42 Pages) HOLTEK

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HT46R23

Rev. 1.30

August 17, 2001

In a (7+1) bits mode PWM cycle, the duty cycle of each

modulation cycle is shown in the table.

Parameter

AC (0~1)

Duty Cycle

Modulation cycle i

(i=0~1)

i<AC

DC 1

128

i³AC

128

The modulation frequency, cycle frequency and cycle

duty of the PWM output signal are summarized in the

following table.

PWM

Modulation Frequency

PWM Cycle

Frequency

PWM Cycle

Duty

FSYS/64 for (6+2) bits mode

FSYS/128 for (7+1) bits mode

fSYS/256 [PWM]/256

A/D converter

The 8 channels and 10-bit resolution A/D (9-bit accu-

racy) converter are implemented in this microcontroller.

The reference voltage is VDD. The A/D converter con-

tains 4 special registers which are; ADRL (24H), ADRH

(25H), ADCR (26H) and ACSR (27H). The ADRH and

ADRL are A/D result register higher-order byte and

lower-order byte and are read-only. After the A/D con-

version is completed, the ADRH and ADRL should be

read to get the conversion result data. The ADCR is an

A/D converter control register, which defines the A/D

channel number, analog channel select, start A/D con-

version control bit and the end of A/D conversion flag. If

the users want to start an A/D conversion. Define PB

configuration, select the converted analog channel, and

give START bit a raising edge and falling edge

(0®1®0). At the end of A/D conversion, the EOC bit is

cleared and an A/D converter interrupt occurs (if the A/D

converter interrupt is enabled). The ACSR is A/D clock

setting register, which is used to select the A/D clock

source.

The A/D converter control register is used to control the

A/D converter. The bit2~bit0 of the ADCR are used to

select an analog input channel. There are a total of eight

channels to select. The bit5~bit3 of the ADCR are used

to set PB configurations. PB can be an analog input or

as digital I/O line decided by these 3 bits. Once a PB line

is selected as an analog input, the I/O functions and

pull-high resistor of this I/O line are disabled and the A/D

f SY S /2

PW M

[P W M ] = 1 0 0

[P W M ] = 1 0 1

PW M

[P W M ] = 1 0 2

PW M

[P W M ] = 1 0 3

PW M

P W M cy cl e : 256/ f SY S

P W M m odul at i on per i od : 64/ f SY S

25/ 6 4

26/ 6 4

25/ 6 4

26/ 6 4

25/ 6 4

26/ 6 4

25/ 6 4

26/ 6 4

(6+2) PWM mode

f SY S /2

PW M

[P W M ] = 1 0 0

[P W M ] = 1 0 1

PW M

[P W M ] = 1 0 2

PW M

[P W M ] = 1 0 3

PW M

P W M cy cl e : 256/ f SY S

P W M m odul at i on per i od : 128 / f SY S

50/ 1 2 8

51/ 1 2 8

52/ 1 2 8

50/ 1 2 8

51/ 1 2 8

50/ 1 2 8

51/ 1 2 8

52/ 1 2 8

(7+1) PWM mode

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