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HMC701LP6CE Datasheet(PDF) 15 Page - Analog Devices

Part # HMC701LP6CE
Description  Fractional or Integer Modes
PDF  40 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

HMC701LP6CE Datasheet(HTML) 15 Page - Analog Devices

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For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
15
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Charge Pump Tri-State
De-asserting both upout_en and dnout_en effectively tri-states the charge pump while leaving all other functions
operating internally.
PFD Jitter & Lock Detect Background
in normal phase locked operation the divided Vco signal arrives at the phase detector in phase with the divided
crystal signal, known as the reference signal. Despite the fact that the device is in lock, the phase of the Vco signal
and the reference signal vary in time due to the phase noise of the crystal and Vco oscillators, the loop bandwidth
used and the presence of fractional modulation or not. the total integrated noise on the Vco path normally dominates
the variations in the two arrival times at the phase detector if fractional modulation is turned off.
if we wish to detect if the Vco is in lock or not we need to distinguish between normal phase jitter when in lock and
phase jitter when not in lock.
First, we need to understand what is the jitter of the synthesizer, measured at the phase detector in integer or fractional
modes.
the standard deviation of the arrival time of the Vco signal, or the jitter, in integer mode may be estimated with a
simple approximation if we assume that the locked Vco has a constant phase noise, Ф2 (ƒ0), at offsets less than
the loop 3 dB bandwidth and a 20 dB per decade roll off at greater offsets. the simple locked Vco phase noise
approximation is shown on the left of Figure 10.
Figure 10. Synthesizer Phase Noise & Jitter
With this simplification the single sideband integrated Vco phase noise, Ф2 , in rads2 at the phase detector is given by
(EQ 9)
where
Ф2 SSB(ƒ0) is the single sideband phase noise in rads2/Hz inside the loop bandwidth, B is the 3 dB corner frequency of
the closed loop PLL and n is the division ratio of the prescaler
the rms phase jitter of the Vco in rads, Ф , results from the power sum of the two sidebands:
Ф = √ 2Ф
2
SSB
(EQ 10)
Since the simple integral of (EQ 9) is just a product of constants, we can easily do the integral in the log domain.
For example if the Vco phase noise inside the loop is -100 dBc/Hz at 10 kHz offset and the loop bandwidth is
100 kHz, and the division ratio n=100, then the integrated single sideband phase noise at the phase detector in dB is
given by Ф2dB = 10log (Ф2(ƒ0)Bπ ⁄ n2) = -100 + 50 + 5 - 40 = -85 dBrads, or equivalently Ф = 10-82/20 = 56 urads rms or
3.2 milli-degrees rms.
While the phase noise reduces by a factor of 20logn after division to the reference, the jitter is a constant.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D



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