For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

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27

HMC701LP6CE

v09.1112

8 GHz 16-BIT FRACTIONAL-N PLL

a typical WritE cycle is shown in Figure 19.

a. the Master (host) both asserts SEn (Serial Port Enable) and clears SDi to indicate a WritE

cycle, followed by a rising edge of ScLK.

b. the slave (synthesizer) reads SDi on the 1st rising edge of ScLK after SEn. SDi low initiates

the WritE cycle (/Wr)

c. Host places the six address bits on the next six falling edges of ScLK, MSB first.

d. Slave registers the address bits in the next six rising edges of ScLK (2-7).

e. Host places the 24 data bits on the next 24 falling edges of ScK, MSB first .

f. Slave registers the data bits on the next 24 rising edges of ScK (8-31).

g. SEn is de-asserted on or after the 32nd falling edge of ScLK.

Figure 19. Serial Port Timing Diagram - WRITE

Main Serial Port READ Operation

aVDD = DVDD = 3V ±10%, aGnD = DGnD = 0V

Table 5. Timing Characteristics

Parameter

Conditions

Min.

Typ.

Max

Units

SEn to ScLK setup time

8

nsec

SDi to ScLK setup time

10

nsec

ScLK to SDi hold time

10

nsec

ScLK high duration

8

nsec

ScLK low duration

8

nsec

SEn High duration

640

nsec

SEn Low duration

20

nsec

ScLK to SDo delay

8ns+0.2ns/pF

nsec

recovery time

10

nsec

the synthesizer uses the multi-purpose pin, LD_SDO, for both Lock Detect and Serial Data out (SDo) functions. the

Data output pin is muxed with the Lock Detect function. if both of the registers are cleared, then the pin is exclusively

SDo. if automux is enabled, the pin switches to SDo when the rD function is sensed on the 1st rising edge of ScLK.

if lkd_to_sdo_always is set, then the pin LD_SDO is dedicated for Lock Detect only, and it is not possible to read from

the synthesizer.

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