For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

31

HMC702LP6CE

v10.0812

14 GHz 16-BIT FRACTIONAL-N PLL

Table 21. Reg 0Fh Integer Division Register

Bit

Type

Name

Default

Description

15:0

r/W

dsm_intg

c8h

unsigned integer portion of Vco divider value,

Table 22. Reg 10h Fractional Division Register

Bit

Type

Name

Default

Description

23:0

r/W

dsm_frac

0

unsigned fractional portion of Vco divider also

Table 23. Reg 11h Seed Register

Bit

Type

Name

Default

Description

23:0

r/W

dsm_seed

0

Unsigned seed value for Δ∑ modulator

Sets the start phase of the modulator. Use a

random , non-repeating number for best results

(examples: 3a1953h, DEaDBEh, 50894ch)

Table 24. Reg 12h Delta Sigma Modulator Register

Bit

Type

Name

Default

Description

0

r/W

dsm_ref_clk_select

0

use reference instead of divider Program 0

1

r/W

dsm_invert_clk_sd3

1

invert Δ∑ clk

2

r/W

dsm_invert_clk_rph

0

inverts the ref clock phase

3

r/W

dsm_integer_mode

0

1- enables integer Mode, bypasses the Δ∑

modulator, leaves it running

see also dsm_rstb reg01h<13> to disable the

modulator

4

r/W

reserved

0

5

r/W

reserved

0

6

r/W

dsm_xref_sin_select

0

when xref is selected specifies that the sine

source is used

7

r/W

dsm_autoseed

1

automatic seed load when changing the frac

part, uses value in seed

9:8

r/W

dsm_order

2h

Delta-Sigma Modulator configuration:

00-1st order 01-2nd order 10-3rd order Feedback

11-3rd order Feedforward

Use either 10 or 11. For Sweeper operation use

11 only.

Do not use 1st or 2nd order (for test only)

13:10

r/W

dsm_quant_max

3h

max value allowed out of Δ∑ modulator quantizer

limits are +7 to -8, typ ±3 or ±4 Program 3h

17:14

r/W

dsm_quant_min

ch

min value allowed out of Δ∑ modulator quantizer

limits are +7 to -8, typ ±3 or ±4 Program ch

[1] Phase-Error Measurement and compensation in PLL Frequency Synthesizers for FMcW, Sensors—i: context and application, Pichler, Stelzer,

Member, iEEE, Seisenberger, and Vossiek, iEEE transactions on circuits and Systems—i, VoL. 54, no. 5, May 2007

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

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