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15

HMC702LP6CE

v10.0812

14 GHz 16-BIT FRACTIONAL-N PLL

Charge Pump & Phase Frequency Detector (PFD)

the Phase Frequency Detector or PFD has two inputs, one from the reference path divider and one from the Vco path

divider. the PFD compares the phase of the Vco path signal with that of the reference path signal and controls the

charge pump output current as a linear function of the phase difference between the two signals. the output current

varies linearly over a full ±2π radians input phase difference.

PFD Functions

slope Vco

the charge pump from pumping up.

prevents the charge pump from pumping down.

Charge Pump Tri-State

De-asserting both upout_en and dnout_en effectively tri-states the charge pump while leaving all other functions

operating internally.

PFD Jitter & Lock Detect Background

in normal phase locked operation the divided Vco signal arrives at the phase detector in phase with the divided

crystal signal, known as the reference signal. Despite the fact that the device is in lock, the phase of the Vco signal

and the reference signal vary in time due to the phase noise of the crystal and Vco oscillators, the loop bandwidth

used and the presence of fractional modulation or not. the total integrated noise on the Vco path normally dominates

the variations in the two arrival times at the phase detector if fractional modulation is turned off.

if we wish to detect if the Vco is in lock or not we need to distinguish between normal phase jitter when in lock and

phase jitter when not in lock.

First, we need to understand what is the jitter of the synthesizer, measured at the phase detector in integer or fractional

modes.

the standard deviation of the arrival time of the Vco signal, or the jitter, in integer mode may be estimated with a

the loop 3 dB bandwidth and a 20 dB per decade roll off at greater offsets. the simple locked Vco phase noise

approximation is shown on the left of Figure 11.

Figure 11. Synthesizer Phase Noise & Jitter

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