AD9528 datasheet(37/68 Pages) AD

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AD9528

Data Sheet

Rev. C | Page 36 of 67

Communication Cycle—Instruction Plus Data

The unified SPI protocol consists of a two-part communication

cycle. The first part is a 16-bit instruction word that is coincident

with the first 16 SCLK rising edges and a payload. The instruction

word provides the AD9528 serial control port with information

regarding the payload. The instruction word includes the R/W bit

that indicates the direction of the payload transfer (that is, a

read or write operation). The instruction word also indicates

the starting register address of the first payload byte.

Write

If the instruction word indicates a write operation, the payload

is written into the serial control port buffer of the AD9528.

Data bits are registered on the rising edge of SCLK. Generally, it

does not matter what data is written to blank registers; however,

it is customary to use 0s. Note that there may be reserved registers

with default values not equal to 0x00; however, every effort was

made to avoid this.

Most of the serial port registers are buffered and data written

into these buffered registers does not take effect immediately.

An additional operation is needed to transfer buffered serial

control port contents to the registers that actually control the

device. This transfer is accomplished with an IO_UPDATE

operation, which is performed in one of two ways. One method

is to write a Logic 1 to Register 0x000F, Bit 0 (this bit is an

autoclearing bit). The user can change as many register bits as

desired before executing an IO_UPDATE. The IO_UPDATE

operation transfers the buffer register contents to their active

Read

If the instruction word indicates a read operation, the next

N × 8 SCLK cycles clock out the data starting from the address

specified in the instruction word. N is the number of data bytes

read. The readback data is driven to the pin on the falling edge

and must be latched on the rising edge of SCLK. Blank registers

are not skipped over during readback.

A readback operation takes data from either the serial control

port buffer registers or the active registers, as determined by

SPI Instruction Word (16 Bits)

The MSB of the 16-bit instruction word is R/W, which indicates

whether the instruction is a read or a write. The next 15 bits are

the register address (A14 to A0), which indicates the starting

that A14 and A13 are ignored and treated as zeros in the

AD9528 because there are no registers that require more than

13 address bits.

SPI MSB-/LSB-First Transfers

The AD9528 instruction word and payload can be MSB first or

LSB first. The default for the AD9528 is MSB first. The LSB first

mode can be set by writing a 1 to Register 0x0000, Bit 1 and Bit 6.

Immediately after the LSB first bit is set, subsequent serial control

port operations are LSB first.

Address Ascension

If the address ascension bits (Register 0x0000, Bit 2 and Bit 5)

are zero, the serial control port register address decrements

from the specified starting address toward Address 0x0000.

If the address ascension bits (Register 0x0000, Bit 2 and Bit 5)

are one, the serial control port register address increments from

the starting address toward Address 0x1FFF. Reserved addresses

are not skipped during multibyte input/output operations;

therefore, write the default value to a reserved register and 0s to

unmapped registers. Note that it is more efficient to issue a new

write command than to write the default value to more than

two consecutive reserved (or unmapped) registers.

Table 25. Streaming Mode (No Addresses Skipped)

Address Ascension

Stop Sequence

Increment

0x0000…0x1FFF

Decrement

0x1FFF…0x0000

Table 26. Serial Control Port, 16-Bit Instruction Word

MSB

LSB

I15

I14

I13

I12

I11

I10

R/W

A14

A13

A12

A11

A10

Figure 40. Serial Control Port Write—MSB First, Address Decrement, Two Bytes of Data

SCLK DON'T CARE

SDIO

A12

A13

A14

R/W

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

DON'T CARE

16-BIT INSTRUCTION HEADER

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