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AD9528 Datasheet(PDF) 66 Page - Analog Devices

Part # AD9528
Description  Maximum output frequency
PDF  68 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9528 Datasheet(HTML) 66 Page - Analog Devices

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Data Sheet
AD9528
Rev. C | Page 65 of 67
STATUS CONTROL (REGISTER 0x0505 TO REGISTER 0x0509)
Table 67. Status Control Signals
Address
Bits
Bit Name
Description
0x0505
[7:0]
Status Monitor 0 control
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mux Out
0
0
0
0
0
0
GND
0
0
0
0
0
1
PLL1 and PLL2 locked
0
0
0
0
1
0
PLL1 locked
0
0
0
0
1
1
PLL2 locked
0
0
0
1
0
0
Both references are missing (REFA and REFB)
0
0
0
1
0
1
Both references are missing and PLL2 is locked
0
0
0
1
1
0
REFB selected (applies only to auto select mode)
0
0
0
1
1
1
REFA is correct
0
0
1
0
0
0
REFB is correct
0
0
1
0
0
1
PLL1 in Holdover
0
0
1
0
1
0
VCXO is correct
0
0
1
0
1
1
PLL1 feedback is correct
0
0
1
1
0
0
PLL2 feedback clock is correct
0
0
1
1
0
1
Fast lock in progress
0
0
1
1
1
0
REFA and REFB are correct
0
0
1
1
1
1
All clocks are correct
0
1
0
0
0
0
PLL1 feedback divide by 2
0
1
0
0
0
1
PLL1 PFD down divide by 2
0
1
0
0
1
0
PLL1 REF divide by 2
0
1
0
0
1
1
PLL1 PFD up divide by 2
0
1
0
1
0
0
GND
0
1
0
1
0
1
GND
0
1
0
1
1
0
GND
0
1
0
1
1
1
GND
Note that all bit combinations after 010111 are reserved
0x0506
[7:0]
Status Monitor 1 control
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mux Out
0
0
0
0
0
0
GND
0
0
0
0
0
1
PLL1 and PLL2 locked
0
0
0
0
1
0
PLL1 locked
0
0
0
0
1
1
PLL2 locked
0
0
0
1
0
0
Both references are missing (REFA and REFB)
0
0
0
1
0
1
Both references are missing and PLL2 is locked
0
0
0
1
1
0
REFB selected (applies only to auto select mode)
0
0
0
1
1
1
REFA is correct
0
0
1
0
0
0
REFB is correct
0
0
1
0
0
1
PLL1 in Holdover
0
0
1
0
1
0
VCXO is correct
0
0
1
0
1
1
PLL1 feedback is correct
0
0
1
1
0
0
PLL2 feedback clock is correct
0
0
1
1
0
1
Fast Lock in Progress
0
0
1
1
1
0
REFA and REFB are correct
0
0
1
1
1
1
All clocks are correct
0
1
0
0
0
0
GND
0
1
0
0
0
1
GND
0
1
0
0
1
0
GND
0
1
0
0
1
1
GND
0
1
0
1
0
0
PLL2 feedback divide by 2
0
1
0
1
0
1
PLL2 PFD down divide by 2



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