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TMS320VC5501 Datasheet(PDF) 97 Page - Texas Instruments |
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TMS320VC5501 Datasheet(HTML) 97 Page - Texas Instruments |
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97 / 193 page  Functional Overview 97 December 2002 − Revised November 2004 SPRS206H 3.11.2.4 Parallel GPIO Enable Register 1 (PGPIOEN1) 15 14 13 12 11 10 9 8 IO31EN IO30EN IO29EN IO28EN IO27EN IO26EN IO25EN IO24EN R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 76 54 32 10 IO23EN IO22EN IO21EN IO20EN IO19EN IO18EN IO17EN IO16EN R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3−37. Parallel GPIO Enable Register 1 Layout (0x4403) Table 3−39. Parallel GPIO Enable Register 1 Bit Field Description† BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION IOxEN 15−0 R/W 0000000000000000 Enable or disable GPIO function of the corresponding I/O pins. See Table 3−35, TMS320VC5501 PGPIO Cross-Reference. IOxEN = 0: GPIO function of corresponding signal is disabled, i.e., the pin goes into a high-impedance state. IOxEN = 1: GPIO function of corresponding signal is enabled, i.e., the signal supports its GPIO function. † x = value from 16 to 31 3.11.2.5 Parallel GPIO Direction Register 1 (PGPIODIR1) 15 14 13 12 11 10 9 8 IO31DIR IO30DIR IO29DIR IO28DIR IO27DIR IO26DIR IO25DIR IO24DIR R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 76 54 32 10 IO23DIR IO22DIR IO21DIR IO20DIR IO19DIR IO18DIR IO17DIR IO16DIR R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3−38. Parallel GPIO Direction Register 1 Layout (0x4404) Table 3−40. Parallel GPIO Direction Register 1 Bit Field Description† BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION IOxDIR 15−0 R/W 0000000000000000 Data direction bits that configure corresponding I/O pins either as inputs or outputs. See Table 3−35, TMS320VC5501 PGPIO Cross-Reference. IOxDIR = 0: Configure corresponding pin as an input. IOxDIR = 1: Configure corresponding pin as an output. † x = value from 16 to 31 |
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