TMS320VC5501 datasheet(98/193 Pages) TI

98 / 193 page

Functional Overview

December 2002 − Revised November 2004

SPRS206H

3.11.2.6

Parallel GPIO Data Register 1 (PGPIODAT1)

IO31DAT

IO30DAT

IO29DAT

IO28DAT

IO27DAT

IO26DAT

IO25DAT

IO24DAT

R/W, pin

IO23DAT

IO22DAT

IO21DAT

IO20DAT

IO19DAT

IO18DAT

IO17DAT

IO16DAT

R/W, pin

LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.

Figure 3−39. Parallel GPIO Data Register 1 Layout (0x4405)

Table 3−41. Parallel GPIO Data Register 1 Bit Field Description†

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

IOxDAT

15−0

R/W

Depends on the signal level on

the corresponding I/O pin

Data bits used to control the level of the corresponding I/O

pins configured as output pins and to monitor the level of the

corresponding I/O pins configured as input pins.

See Table 3−35, TMS320VC5501 PGPIO Cross-Reference.

If IOxDIR = 0, then:

IOxDAT = 0:

Corresponding I/O pin is read as a low

IOxDAT = 1:

Corresponding I/O pin is read as a high

If IOxDIR = 1, then:

IOxDAT = 0:

Set corresponding I/O pin to low

IOxDAT = 1:

Set corresponding I/O pin to high

† x = value from 16 to 31

TMS320VC5501 Datasheet(PDF) 98 Page - Texas Instruments

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