SN65LVDS1, SN65LVDS2, SN65LVDT2

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SLLS373L – JULY 1999 – REVISED DECEMBER 2014

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are single-channel LVDS buffers. The functionality of

these devices is simple, yet extremely flexible, leading to their use in designs ranging from wireless base stations

to desktop computers. The varied class of potential applications share features and applications discussed in the

paragraphs below.

10.2 Typical Applications

10.2.1 Point-to-Point Communications

The most basic application for LVDS buffers, as found in this data sheet, is for point-to-point communications of

digital data, as shown in Figure 18.

Figure 18. Point-to-Point Topology

A point-to-point communications channel has a single transmitter (driver) and a single receiver. This

communications topology is often referred to as simplex. In Figure 18 the driver receives a single-ended input

signal and the receiver outputs a single-ended recovered signal. The LVDS driver converts the single-ended

input to a differential signal for transmission over a balanced interconnecting media of 100-

Ω characteristic

impedance. The conversion from a single-ended signal to an LVDS signal retains the digital data payload while

translating to a signal whose features are more appropriate for communication over extended distances or in a

noisy environment.

10.2.1.1 Design Requirements

DESIGN PARAMETERS

EXAMPLE VALUE

2.4 to 3.6 V

Driver Input Voltage

0.8 to 5.0 V

Driver Signaling Rate

DC to 400 Mbps

Interconnect Characteristic Impedance

100

Ω

Termination Resistance

100

Ω

Number of Receiver Nodes

1

2.4 to 3.6 V

Receiver Input Voltage

Receiver Signaling Rate

DC to 400 Mbps

Ground shift between driver and receiver

±1 V

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