SN65LVDS1, SN65LVDS2, SN65LVDT2

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SLLS373L – JULY 1999 – REVISED DECEMBER 2014

10.2.1.2.9

Receiver Supply Voltage

The SN65LVDS2 and SN65LVDT2 receivers are operated from a single supply. Like the SN65LVDS1, these

devices can support operation with a supply as low as 2.4 V and as high as 3.6 V. The main effects of low supply

voltage for these LVDS receivers will be seen in the receiver input common-mode range and the receiver output

voltage. We will address these in turn below.

10.2.1.2.10

Receiver Bypass Capacitance

Bypass capacitors recommendations have been discussed above in Driver Bypass Capacitance.

10.2.1.2.11

Receiver Input Common-Mode Range

The SN65LVDS2 and SN65LVDT2 support operation over an input common-mode range that is dependent upon

the device supply voltage. Per the recommended conditions table, we see that operation is supported between 0

V and 0.8 V below the supply rail.

For a supply voltage of 3.3 V, operation is available when the input common-mode voltage is between GND and

2.5 V. The receivers are required to meet sensitivity requirements over the whole common-mode input range.

If we return to the transmitter discussions, we recall that the SN65LVDS1 has an output common-mode range of

1.2 V. Using one of the receivers discussed here, we see that valid operation of the communication link will occur

when the ground difference between transmitter and receiver is within ~±1 V . The use of differential signaling in

LVDS allows operation in an environment where the combination of ground difference and common-mode noise

result in a common-mode difference between transmitter and receiver of 1 V. This 1-V potential difference hints

at the intended application of LVDS circuits.

Standards such as RS-485 support potential differences of almost 10 V, allowing for communication over

distances of greater than 1 km. The intended applications of LVDS devices is more moderate distances, such as

those from chip to chip on a board, board to board in a rack, or from rack to nearby rack. When the 1-V potential

difference is not adequate, yet the high-speed and low voltage features of LVDS are still needed, the designer

can choose from either M-LVDS devices available from TI, or from LVDS devices with extended common-mode

ranges, such as the SN65LVDS33.

10.2.1.2.12

Receiver Input Signal

The LVDS receivers herein comply with the LVDS standard and correctly determine the bus state when the

differential input voltage is greater than 100 mV (HI output) or less than –100 mV (LO output). In addition, the

receivers operate with differential input voltages of up to 600 mV.

10.2.1.2.13

Receiver Output Signal

Receiver outputs comply with LVTTL output voltage standards when the supply voltage is within the range of 3 V

to 3.6 V. When the supply voltage is within the lower range of 2.4 V to 3 V, the high output voltage can be as low

as 1.9 V. If a design intends to operate the receivers with a supply voltage in this lower range, care should be

taken to ensure that the device being driven by these devices will be able to operate without errors with the lower

output voltage.

10.2.1.2.14

Receiver NC Pins

NC (not connected) pins are pins where the die is not physically connected to the lead frame or package. For

optimum thermal performance, a good rule of thumb is to ground the NC pins at the board level.

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Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2