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SN65LVDT2DBVT Datasheet(PDF) 22 Page - Texas Instruments

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Part # SN65LVDT2DBVT
Description  High-Speed Differential Line Drivers and Receivers
PDF  42 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN65LVDT2DBVT Datasheet(HTML) 22 Page - Texas Instruments

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SN65LVDS1, SN65LVDS2, SN65LVDT2
SLLS373L – JULY 1999 – REVISED DECEMBER 2014
www.ti.com
Figure 20. Controlled-Impedance Transmission Lines
10.2.1.2.7
Termination Resistor
As shown earlier, an LVDS communication channel employs a current source driving a transmission line which is
terminated with a resistive load. This load serves to convert the transmitted current into a voltage at the receiver
input. To ensure incident wave switching (which is necessary to operate the channel at the highest signaling
rate), the termination resistance should be matched to the characteristic impedance of the transmission line. The
designer should ensure that the termination resistance is within 10% of the nominal media characteristic
impedance. If the transmission line is targeted for 100-
Ω impedance, the termination resistance should be
between 90
Ω and 110 Ω.
The line termination resistance should be located as close as possible to the receiver, thereby minimizing the
stub length from the resistor to the receiver. The limiting case would be to incorporate the termination resistor
into the receiver, which is exactly what is offered with the SN65LVDT2. The SN65LVDT2 provides all the
functionality and performance of the SN65LVDS2 receiver, with the added feature of an integrated termination
load.
While we talk in this section about point-to-point communications, a word of caution is useful when a multidrop
topology is used. In such topologies, line termination resistors are to be located only at the end(s) of the
transmission line. In such an environment, SN65LVDS2 receivers could be used for loads branching off the main
bus, with an SN65LVDT2 used only at the bus end.
10.2.1.2.8
Driver NC Pins
NC (not connected) pins are pins where the die is not physically connected to the lead frame or package. For
optimum thermal performance, a good rule of thumb is to ground the NC pins at the board level.
22
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Copyright © 1999–2014, Texas Instruments Incorporated
Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2



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