SN65LVDS1, SN65LVDS2, SN65LVDT2

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SLLS373L – JULY 1999 – REVISED DECEMBER 2014

Layout Guidelines (continued)

12.1.2 Dielectric Type and Board Construction

The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually

provides adequate performance for use with LVDS signals. If rise or fall times of TTL/CMOS signals are less

than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350

or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters

pertaining to the board construction that can affect performance. The following set of guidelines were developed

experimentally through several designs involving LVDS devices:

•

Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz

•

All exposed circuitry should be solder-plated (60/40) to 7.62

μm or 0.0003 in (minimum).

•

Copper plating should be 25.4

μm or 0.001 in (minimum) in plated-through-holes.

•

Solder mask over bare copper with solder hot-air leveling

12.1.3 Recommended Stack Layout

Following the choice of dielectrics and design specifications, you must decide how many levels to use in the

stack. To reduce the TTL/CMOS to LVDS crosstalk, it is a good practice to have at least two separate signal

planes as shown in Figure 26.

Figure 26. Four-Layer PCB Board

NOTE

The separation between layers 2 and 3 should be 127

μm (0.005 in). By keeping the

power and ground planes tightly coupled, the increased capacitance acts as a bypass for

transients.

One of the most common stack configurations is the six-layer board, as shown in Figure 27.

Figure 27. Six-Layer PCB Board

In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one

ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer

board is preferable, because it offers the layout designer more flexibility in varying the distance between signal

layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6.

12.1.4 Separation Between Traces

The separation between traces depends on several factors; however, the amount of coupling that can be

tolerated usually dictates the actual separation. Low noise coupling requires close coupling between the

differential pair of an LVDS link to benefit from the electromagnetic field cancellation. The traces should be 100-

Ω

differential and thus coupled in the manner that best fits this requirement. In addition, differential pairs should

have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal

reflection.

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