LVDS

1A

C

200 ps

0.001 F

0.2V

æ

ö

=

´

=

m

ç

÷

è

ø

Maximum Step Change Supply Current

chip

Rise Time

Maximum Power Supply Noise

I

C

T

V

D

æ

ö

=

´

ç

÷

D

è

ø

SN65LVDS1, SN65LVDS2, SN65LVDT2

SLLS373L – JULY 1999 – REVISED DECEMBER 2014

www.ti.com

10.2.1.2 Detailed Design Procedure

10.2.1.2.1

Driver Supply Voltage

The SN65LVDS1 driver is operated from a single supply. The device can support operation with a supply as low

as 2.4 V and as high as 3.6 V. The driver output voltage is dependent upon the chosen supply voltage. As shown

in Driver Electrical Characteristics, the differential output voltage is nominally 350 mV over the complete output

range. The minimum output voltage stays within the specified LVDS limits (247 mV to 454 mV) for a 3.3-V

supply. If the supply range is between 2.4 V and 3 V, the minimum output voltage may be as low as 200 mV. If a

communication link is designed to operate with a supply within this lower range, the channel noise margin will

need to be looked at carefully to ensure error-free operation.

10.2.1.2.2

Driver Bypass Capacitance

Bypass capacitors play a key role in power distribution circuitry. Specifically, they create low-impedance paths

between power and ground. At low frequencies, a good digital power supply offers very low-impedance paths

between its terminals. However, as higher frequency currents propagate through power traces, the source is

quite often incapable of maintaining a low-impedance path to ground. Bypass capacitors are used to address this

shortcoming. Usually, large bypass capacitors (10

μF to 1000 μF) at the board-level do a good job up into the

kHz range. Due to their size and length of their leads, they tend to have large inductance values at the switching

frequencies of modern digital circuitry. To solve this problem, one must resort to the use of smaller capacitors

(nF to

μF range) installed locally next to the integrated circuit.

Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass

capacitors in high-speed environments, because their lead inductance is about 1 nH. For comparison purposes,

a typical capacitor with leads has a lead inductance around 5 nH.

The value of the bypass capacitors used locally with LVDS chips can be determined by the following formula

according to Johnson, equations 8.18 to 8.21. A conservative rise time of 200 ps and a worst-case change in

supply current of 1 A covers the whole range of LVDS devices offered by Texas Instruments. In this example, the

maximum power supply noise tolerated is 200 mV; however, this figure varies depending on the noise budget

(1)

(2)

The following example lowers lead inductance and covers intermediate frequencies between the board-level

capacitor (>10 µF) and the value of capacitance found above (0.001 µF). You should place the smallest value of

capacitance as close as possible to the chip.

Figure 19. Recommended LVDS Bypass Capacitor Layout

(1)

Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number

013395724.

20

Submit Documentation Feedback

Copyright © 1999–2014, Texas Instruments Incorporated

Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2