SN65LVDS1, SN65LVDS2, SN65LVDT2

www.ti.com

SLLS373L – JULY 1999 – REVISED DECEMBER 2014

10.2.3.2 Detailed Design Procedure

10.2.3.2.1

Interconnecting Media

The interconnect in a multidrop system differs considerably from a point-to-point system. While point-to-point

interconnects are straightforward, and well understood, the bus type architecture encountered with multidrop

systems requires more careful attention. We will use Figure 22 above to explore these details.

The most basic multidrop system would include a single driver, located at a bus origin, with multiple receiver

nodes branching off the main line, and a final receiver at the end of the transmission line, co-located with a bus

termination resistor. While this would be the most basic multidrop system, it has several considerations not yet

explored.

The location of the transmitter at one bus end allows the design concerns to be simplified, but this comes at the

cost of flexibility. With a transmitter located at the origin, a single bus termination at the far-end is required. The

far-end termination absorbs the incident traveling wave. The flexibility lost with this arrangement is thus: if the

single transmitter needed to be relocated on the bus, at any location other than the origin, we would be faced

with a bus with one open-circuited end, and one properly terminated end. Locating the transmitter say in the

middle of the bus may be desired to reduce (by ½) the maximum flight time from the transmitter to receiver.

Another new feature in Figure 22 is clear in that every node branching off the main line results in stubs. The

stubs should be minimized in any case, but have the unintended effect of locally changing the loaded impedance

of the bus.

To a good approximation, the characteristic transmission line impedance seen into any cut point in the unloaded

multipoint or multidrop bus is defined by

√L/C, where L is the inductance per unit length and C is the capacitance

per unit length. As capacitance is added to the bus in the form of devices and interconnections, the bus

characteristic impedance is lowered. This may result in signal reflections from the impedance mismatch between

the unloaded and loaded segments of the bus.

If the number of loads is constant and can be distributed evenly along the line, reflections can be reduced by

changing the bus termination resistors to match the loaded characteristic impedance. Normally, the number of

loads are not constant or distributed evenly and the reflections resulting from any mismatching must be

accounted for in the noise budget.

10.2.3.3 Application Curve

Figure 23. Typical Driver Output Eye Pattern in Multidrop System

Copyright © 1999–2014, Texas Instruments Incorporated

Submit Documentation Feedback

25

Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2