TMS320VC5421 datasheet(30/104 Pages) TI1

30 / 104 page

Functional Overview

December 1999 − Revised October 2008

SPRS098D

3.1.6 Program Memory

The program memory is accessible on multiple pages, depending on the XPC value. Within these pages,

memory is accessible, depending on the address range.

•

Access in the lower 32K of each page is dependent on the state of OVLY.

−

OVLY = 0 − Program memory is accessed externally for all values of XPC.

−

OVLY = 1 − Program memory is accessed from local data/program DARAM for all values of XPC.

•

Access in the upper 32K of each page is dependent on the state of MP/MC and the value of XPC.

−

MP/MC = 0 − Program memory is accessed internally from two-way shared DARAM for XPC = 0−3.

Program memory is accessed externally for XPC = 4−127.

−

MP/MC = 1 − Program memory is accessed externally for all values of XPC.

3.1.7 Data Memory

The data memory space is a single page of 64K. Access is dependent on the address range. Access in the

lower 32K of data memory is always from local DARAM.

Access in the upper 32K of data memory is dependent on the state of DROM.

•

DROM = 0 − Data memory is accessed externally

•

DROM = 1 − Data memory is accessed internally from local SARAM

3.1.8 I/O Memory

The I/O space is a single page of 64K. Access is always external.

When XIO = 0 and an access to external memory is attempted, any write is ignored and any read is an unknown

value.

3.2

Multicore Reset Signals

The 5421 device includes three reset signals: A_RS, B_RS, and HPIRS. The A_RS and B_RS pins function

as the CPU reset signal for subsystem A and subsystem B, respectively. These signals reset the state of the

CPU registers and upon release, initiate the reset function. Additionally, the A_RS signal resets the on-chip

PLL and initializes the CLKMD register to bypass mode.

The HPI reset signal (HPIRS) places the HPI peripheral into a reset state. It is necessary to wait three clock

cycles after the rising edge of HPIRS before performing an HPI access. The HPIRS signal also resets the PLL

by turning off the PLL and initializing the CLKMD register to bypass mode.

3.3

Bootloader

The on-chip bootloader is used to automatically transfer user code from an external source to anywhere in

program memory after reset. The XIO pin is sampled during a hardware reset and the results indicate the

operating mode as shown in Table 3−2.

Table 3−2. Bootloader Operating Modes

XIO

AFTER RESET

HPI mode, bootload is controlled by host. The external host holds the 5421 in reset while it loads the on-chip

memory of one or both subsystems as determined by the SELA/B pin.

The host can release the 5421 from reset by either of the following methods:

If the A_RS/B_RS pins are held low while HPIRS transitions from low to high, the subsystem cores reset will

be controlled by the A_RS/B_RS pins. When the host has finished downloading code, it drives A_RS/B_RS

high to release the cores from reset.

If the A_RS/B_RS pins are held high while HPIRS transitions from low to high, the subsystems stay in reset

until a HPI data write to address 0x2F occurs. This means the host can download code to subsystem A and

then release core A from reset by writing any data to core A address 0x2F via the HPI. The host can then repeat

the sequence for core B. This mode allows the host to control the 5421 reset without additional hardware.

XIO mode. ROM is mapped in, if ROMEN pin = 1 during reset.

TMS320VC5421 Datasheet(PDF) 30 Page - Texas Instruments

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