TMS320VC5421 datasheet(31/104 Pages) TI1

31 / 104 page

Functional Overview

December 1999 − Revised October 2008

SPRS098D

The 5421 bootloader provides the following options for the source of code to download:

•

Parallel from 8-bit or 16-bit-wide EPROM

•

Serial boot from McBSPs, 8-bit mode

GPIO register bit 7 (ROMEN) is used to enable/disable the ROM after reset. The ROMEN bit reflects the status

of the ROMEN/GPIO0 pin for each core. ROMEN = 1 indicates that the ROM and the 8K-word program

memory block (00 E000h−00 FFFFh) are not available for a CPU write. When ROMEN = 0, this 8K-word

program memory is available and the ROM is disabled.

A combination of interrupt flags and the bit values of an external memory location determine the selection of

the various boot options.

3.4

External Interface (XIO)

The external interface (XIO) supports the 5421 master boot modes and other external accesses. Its features

include:

•

Multiplexed with the HPI pins

•

Selection of XIO or HPI mode is determined by a dedicated pin (XIO)

•

Provides 512K words of external program space, 64K words of external data space, and 64K words of

external I/O space.

•

Different boot modes are selectable by the XIO, HMODE, and A_RS/B_RS pins.

•

After reset, the control register bit ROMEN is always preset to 1.

While XIO = 0 during reset, host HPI mode is on, the host sees all RAM, and ROM is disabled. A host write

to 002Fh releases the CPUs from reset; the 002Fh write by the host clears the ROMEN bit in the GPIO register.

While XIO = 1 and ROMEN = 1 during reset, the CPU starts from ROM (0FF80h) to do boot selection. After

branching to non-ROM area, the code changes the ROMEN bit to enable the RAM area occupied by ROM.

While XIO = 1 and ROMEN = 0 during reset, the CPU starts from external (0FF80h) to do boot selection.

Table 3−3 provides a complete description of HMODE, SELA/B, and XIO pin functionality.

Table 3−3. XIO/HPI Modes

HMODE

SELA/B

HPI MODES (XIO = 0)

XIO MODES (XIO = 1)

HPI muxed address/data subsystem A slave to host

SELA/B pin is multiplexed as PPA18 output.

HPI muxed address/data subsystem B slave to host

SELA/B pin is multiplexed as PPA18 output.

HPI non-muxed address/data subsystem A slave to host

SELA/B pin is multiplexed as PPA18 output.

HPI non-muxed address/data subsystem B slave to host

SELA/B pin is multiplexed as PPA18 output.

3.5

On-Chip Peripherals

All the 54x devices have the same CPU structure; however, they have different on-chip peripherals connected

to their CPUs. The on-chip peripheral options provided are:

•

Software-programmable wait-state generator

•

Programmable bank-switching

•

Parallel I/O ports

•

Multichannel buffered serial ports (McBSPs)

•

A hardware timer

•

A software-programmable clock generator using a phase-locked loop (PLL)

TMS320VC5421 Datasheet(PDF) 31 Page - Texas Instruments

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