TMS320VC5421 datasheet(45/104 Pages) TI1

45 / 104 page

Functional Overview

December 1999 − Revised October 2008

SPRS098D

DMA_ARB

CPU_ARB

EMIF

Controller

GRANT

DMA_REQ_B

DMA_GRANT_B

XDMA

(DSP

Subsystem B)

XIO

Grant

XIO

Req

Core

SEL=1

VCC

GPIO Control

(DSP Subsystem B)

54x cLEAD CPU

(DSP Subsystem B)

Req

Grant

XIO

SEL=0

Core

54x cLEAD CPU

DMA_REQUEST

GRANT_A

GPIO Control

(DSP Subsystem A)

Subsystem A)

(DSP

XDMA

DMA_REQ_A

DMA_GRANT_A

DMA_REQUEST

GRANT_B

SEL

XIO

XHOLD

XHOLDA

XDMA

XCPU

XDMA

XCPU

Figure 3−15. Arbitration Between XIO and xDMA for External Access

The HM bit in the ST1 indicates whether the processor continues internal execution when acknowledging an

active HOLD signal.

•

HM = 0, the processor continues execution from internal program memory but places its external interface

in the high-impedance state.

•

When HM = 1, the processor halts internal execution.

To ensure that proper arbitration occurs, the HM bit should be set to 0 in the memory-mapped ST1 registers

for both CPUs.

To allow the DMA access to extended data pages, the SLAXS and DLAXS bits are added to the DMMCRn

registers. For a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced

Peripherals (literature number SPRU302).

9876

210

AUTO

INIT

DINM

IMOD

MOD

SLAXS

SIND

DMS

DLAXS

DIND

DMD

Figure 3−16. DMA Transfer Mode Control Register (DMMCRn)

TMS320VC5421 Datasheet(PDF) 45 Page - Texas Instruments

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