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TMS320VC5421 Datasheet(PDF) 82 Page - Texas Instruments

Part # TMS320VC5421
Description  Fixed-Point Digital Signal Processor
PDF  104 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320VC5421 Datasheet(HTML) 82 Page - Texas Instruments

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Electrical Specifications
82
December 1999 − Revised October 2008
SPRS098D
Table 5−22. McBSP
Transmit and Receive Switching Characteristics†
PARAMETER
MIN
MAX
UNIT
tc(BCKRX)
Cycle time, BCLKR/X
BCLKR/X int
4H
ns
tw(BCKRXH)
Pulse duration, BCLKR/X high
BCLKR/X int
D−4‡
D+1‡
ns
tw(BCKRXL)
Pulse duration, BCLKR/X low
BCLKR/X int
C−4‡
C+1‡
ns
td(BCKRH-BFRV)
Delay time, BCLKR high to internal BFSR valid
BCLKR int
−3
3
ns
td(BCKXH-BFXV)
Delay time, BCLKX high to internal BFSX valid
BCLKX int
−3
8
ns
td(BCKXH-BFXV)
Delay time, BCLKX high to internal BFSX valid
BCLKX ext
2
15
ns
tdis(BCKXH-BDXHZ) Disable time, BCLKX high to BDX high impedance following last data bit
BCLKX int
−8
3
ns
tdis(BCKXH-BDXHZ) Disable time, BCLKX high to BDX high impedance following last data bit
BCLKX ext
1
12
ns
Delay time, BCLKX high to BDX valid. This applies to all bits except the first
BCLKX int
−1
11
Delay time, BCLKX high to BDX valid. This applies to all bits except the first
bit transmitted.
BCLKX ext
4
20
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid.§
DXENA = 0
BCLKX int
11
ns
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid.§
Only applies to first bit transmitted when in Data Delay 1
DXENA = 0
BCLKX ext
20
ns
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
BCLKX int
4H+6
or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
BCLKX ext
4H+15
Enable time, BCLKX high to BDX driven.§
DXENA = 0
BCLKX int
5
ten(BCKXH-BDX)
Enable time, BCLKX high to BDX driven.§
Only applies to first bit transmitted when in Data Delay 1
DXENA = 0
BCLKX ext
16
ns
ten(BCKXH-BDX)
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
BCLKX int
4H
ns
or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
BCLKX ext
4H+12
Delay time, BFSX high to BDX valid.§
DXENA = 0
BFSX int
9
td(BFXH-BDXV)
Delay time, BFSX high to BDX valid.§
Only applies to first bit transmitted when in Data Delay 0
DXENA = 0
BFSX ext
15
ns
td(BFXH-BDXV)
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode.
DXENA = 1
BFSX int
4H
ns
(XDATDLY=00b) mode.
DXENA = 1
BFSX ext
4H+15
Enable time, BFSX high to BDX driven.§
DXENA = 0
BFSX int
2
ten(BFXH-BDX)
Enable time, BFSX high to BDX driven.§
Only applies to first bit transmitted when in Data Delay 0
DXENA = 0
BFSX ext
14
ns
ten(BFXH-BDX)
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode
DXENA = 1
BFSX int
4H−1
ns
(XDATDLY=00b) mode
DXENA = 1
BFSX ext
2H+5
† Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡ T=BCLKRX period = (1 + CLKGDV) * 2H
C=BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D=BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ See the TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302) for a description of the DX enable
(DXENA) and data delay features of the McBSP.



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