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ST10F273Z4 Datasheet(PDF) 92 Page - STMicroelectronics |
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ST10F273Z4 Datasheet(HTML) 92 Page - STMicroelectronics |
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92 / 188 page  System reset ST10F273Z4 92/188 Refer to next Figures 23 and 24 for unidirectional SW reset timing, and to Figures 25, 26 and 27 for bidirectional. 20.5 Watchdog timer reset When the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after the programmed wait states. When READY is sampled inactive (high) after the programmed wait states the running external bus cycle is aborted. Then the internal reset sequence is started. Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared (that is written at ‘1’). A Watchdog reset is always taken as synchronous: there is no influence on Watchdog Reset behavior with RPD status. In case Bidirectional Reset is selected, a Watchdog Reset event pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled low even though Bidirectional Reset is selected. Refer to next Figures 23 and 24 for unidirectional SW reset timing, and to Figures 25, 26 and 27 for bidirectional. Figure 23. SW / WDT unidirectional RESET (EA = 1) P0[7:2] not transparent P0[12:8] transparent not t. P0[1:0] not t. not transparent RST 1024 TCL RSTOUT RSTIN IBUS-CS 7 TCL P0[15:13] not transparent FLARST ≤ 1 ms (Internal) ≤ 2 TCL |
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