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FDMS8680 Datasheet(PDF) 2 Page - Texas Instruments |
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FDMS8680 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 27 page ![]() TPS51218 SLUS935B – MAY 2009 – REVISED FEBRUARY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION ORDERING DEVICE OUTPUT MINIMUM TA PACKAGE PINS NUMBER SUPPLY QUANTITY TPS51218DSCR 10 Tape and reel 3000 –40°C to 85°C Plastic SON PowerPAD TPS51218DSCT 10 Mini reel 250 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT VBST –0.3 to 37 VBST(3) –0.3 to 7 Input voltage range(2) V SW –5 to 30 V5IN, EN, TRIP, VFB, RF –0.3 to 7 DRVH –5 to 37 DRVH(3) –0.3 to 7 DRVH(3), pulse width < 20 ns –2.5 to 7 Output voltage range(2) V DRVL –0.5 to 7 DRVL, pulse width < 20 ns –2.5 to 7 PGOOD –0.3 to 7 TJ Junction temperature range 150 °C TSTG Storage temperature range –55 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the network ground terminal unless otherwise noted. (3) Voltage values are with respect to the SW terminal. DISSIPATION RATINGS 2-oz. trace and copper pad with solder. PACKAGE TA < 25°C DERATING FACTOR TA = 85°C POWER RATING ABOVE TA = 25°C POWER RATING 10-pin DSC(1) 1.54 W 15 mW/ °C 0.62 W (1) Enhanced thermal conductance by thermal vias is used beneath thermal pad as shown in Land Pattern information. 2 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 |
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