AD7183 datasheet(37/40 Pages) AD

37 / 40 page

REV. 0

ADV7183

–37–

Appendix

BOARD DESIGN AND LAYOUT CONSIDERATIONS

The ADV7183 is a highly integrated circuit containing both preci-

sion analog and high-speed digital circuitry. It has been designed to

minimize interference effects on the integrity of the analog circuitry

by the high-speed digital circuitry. It is imperative that these same

design and layout techniques be applied to the system level design

such that high speed and accurate performance are achieved. Figure

30 shows the recommended analog circuit layout.

The layout should be optimized for lowest noise on the ADV7183

power and ground lines by shielding the digital inputs and provid-

ing good decoupling. The lead length between groups of VDD and

GND pins should be minimized to reduce inductive ringing.

Ground Planes

The ground plane should be split into two, one analog and one

digital. They should be joined directly under the ADV7183.

The analog ground return path should be through the digital

(the digital ground is connected to the analog ground and also

the system ground, whereas the analog ground is only connected

to the digital ground; this will ensure only analog current will flow

in the analog ground).

Power Planes

The ADV7183 and any associated analog circuitry should have

its own power planes, referred to as the analog and digital

power planes. These power planes should be connected to the

regular PCB power plane (VCC) at a single point through a ferrite

bead. This bead should be located within three inches of the

ADV7183.

The PCB power plane should provide power to all digital logic on

the PC board and the digital power pins on the ADV7183, and

the analog power plane should provide power to all analog power

pins on the ADV7183.

Plane-to-plane noise coupling can be reduced by ensuring that

portions of the regular PCB power and ground planes do not

overlay portions of the analog power plane, unless they can be

arranged so the plane-to-plane noise is common-mode.

Supply Decoupling

For optimum performance, bypass capacitors should be installed

using the shortest leads possible, consistent with reliable operation,

to reduce the lead inductance. Best performance is obtained with

0.1

µF ceramic capacitor decoupling. Each group of power pins

on the ADV71783 must have at least one 0.1

µF decoupling

capacitor to its corresponding ground. These capacitors should

be placed as close as possible to the device.

It is important to note that while the ADV7183 contains cir-

cuitry to reject power supply noise, this rejection decreases with

frequency. If a high-frequency switching power supply is used,

the designer should pay close attention to reducing power sup-

ply noise and consider using a three-terminal voltage regulator

for supplying power to the analog power plane.

Digital Signal Interconnect

The digital inputs and outputs to and from the ADV7183 should

be isolated as much as possible from the analog inputs and other

analog circuitry. Also, these input signals should not overlay the

analog power plane.

Due to the high clock rates involved, long clock lines to and

from the ADV7183 should be avoided to reduce noise pickup.

Any series termination resistors (typically 33

Ω) for the digital

inputs should be connected to the high-speed digital outputs.

Analog Signal Interconnect

The ADV7183 should be located as close as possible to the

input connectors to minimize noise pickup and reflections due

to impedance mismatch.

The video input signals should overlay the ground plane, and

not the analog power plane, to maximize the high-frequency

power supply rejection.

Digital outputs, especially pixel data Inputs and clocking sig-

nals, should never overlay any of the analog signal circuitry and

should be kept as far away as possible.

The ADV7183 should have no inputs left floating. Any inputs

that are not required should be tied to ground.

AD7183 Datasheet(PDF) 37 Page - Analog Devices

AD7183 Datasheet(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL