REV. 0

–28–

ADV7183

Table XXIV. Digital Clamp Control 1 Register (Subaddress 15)

Bit Description

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Register Setting

DCCO[11:8]

1

XXXX

Only applicable if DCCM is set to manual offset

mode.

DCFE

2

0

Digital Clamp Operational

1

Digital Clamp Frozen

DCT[1:0]

3

0

0

Slow (TC = 1 second)

0

1

Medium (TC = 0.5 second)

1

0

Fast (TC = 0.1 second)

1

1

Dependent on VID_QUAL

DCCM[7:0]

4

0

Automatic Digital Clamp

1

NOTES

Table XXV. Digital Clamp Control 2 Register (Subaddress 16)

Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

DCCO[7:0]

*

XXXXXXXX

*Digital Color Clamp Offset. Holds the lower 8 bits of the digital offset value which is added to the raw data from the ADC before entering the core. Only applicable if

DCCM is set to manual offset mode.

Table XXVI. Shaping Filter Control Register (Subaddress 17)

Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

YSFM[4:0]

1

00000

Auto Wide Notch

00001

Auto Narrow Notch

00010

SVHS 1

––––––

10010

SVHS 17

10011

PAL NN1

10100

PAL NN2

10101

PAL NN3

10110

PAL WN 1

10111

PAL WN 2

11000

NTSC NN1

11001

NTSC NN2

11010

NTSC NN3

11011

NTSC WN1

11100

NTSC WN2

11101

NTSC WN3

11110

Not Used

11111

SVHS 18

CSFM[2:0]

2

0

0

0

Auto Selection 1.5 MHz

0

0

1

Auto Selection 2.17 MHz

010

SH1

–––

–

110

SH5

111

SH6

NOTES