AD7183 datasheet(38/40 Pages) AD

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REV. 0

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ADV7183

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AVSS

100nF

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AVSS6

AVSS5

AVSS4

AVSS3

AVSS2

AVSS1

DVDDIO DVDD

AVDD

P10

P11

P12

P14

GPO0

GPO2

GPO3

GPO1

P15

P13

DVDD

FERRITE

BEAD

33 F

10 F

DVSS

AVDD

FERRITE

BEAD

33 F

10 F

AVSS

AVSS DVSS

0.1 F

0.01 F

DVSS

0.1 F

0.01 F

AVSS

POWER SUPPLY DECOUPLING

FOR EACH POWER PIN

POWER SUPPLY DECOUPLING

FOR EACH POWER PIN

INPUT

SWITCH OVER

ISO

10 F

0.1 F

AVSS

10 F

0.1 F

AVSS

CAP Y1

CAP Y2

CAP C1

CAP C2

0.1 F

CML

REFOUT

10 F

0.1 F

AVSS

XTAL

XTAL1

33 F

27MHz

DVSS

DVDD

ALSB

SCLK

SDA

RESET

I2C INTERFACE

CONTROL LINE

I2C INTERFACE

CONTROL LINE

100R

DVDD

100nF

DVSS

DVDD

RESET

MULTIFORMAT

PIXEL PORT*

P15–P8: 8-BIT CCIR656 PIXEL DATA @ 27MHz

P7–P0: Cb AND Cr 16-BIT CCIR656 PIXEL DATA @ 13.5MHz

P15–P8: Y1 AND Y2 16-BIT CCIR656 PIXEL DATA @ 13.5MHz

LLC2

LLCREF

LLC

AEF

GL/QCLK/HFF

AFF

27MHz OUTPUT CLOCK

13.5MHz OUTPUT CLOCK

CLOCK REFERENCE O/P

ALMOST EMPTY FIFO O/P

ALMOST FULL FIFO O/P

READ SIGNAL I/P

OUTPUT ENABLE I/P

DATA VALID O/P

GL/QCLK/HFF O/P

VS/

RESET

FIELD

HS/

RESET

HS/

RESET O/P

VS/

RESET O/P

FIELD O/P

PWRDN

POWER-DOWN INPUT

FIFO MANAGEMENT

SIGNALS ONLY USED

IN FIFO MODE;

USE LLC AND GENLOCK

FOR NON-FIFO MODE

ELPF

5.6k

2nF

68pF

AVDD

4.7k

Figure 30. Recommended Analog Circuit Layout

AD7183 Datasheet(PDF) 38 Page - Analog Devices

AD7183 Datasheet(HTML) 38 Page - Analog Devices

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