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ADV7183

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PIN FUNCTION DESCRIPTIONS

Mnemonic

Input/Output

Function

VS/VACTIVE

VS or Vertical Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is an

output signal that indicates a vertical sync with respect to the YUV pixel

data. The active period of this signal is six lines of video long. The polarity

of the VS signal is controlled by the PVS bit. VACTIVE (OM_SEL[1:0] =

1, 0 or 0, 1) is an output signal that is active during the active/viewable

period of a video field. The polarity of VACTIVE is controlled by PVS bit.

HS/HACTIVE

HS or Horizontal Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is a

programmable horizontal sync output signal. The rising and falling edges

can be controlled by HSB[9:0] and HSE[9:0] in steps of 2 LLC1. The polarity

of the HS signal is controlled by the PHS bit. HACTIVE (OM_SEL[1:0] =

1, 0 or 0, 1) is an output signal that is active during the active/viewable

period of a video line. The active portion of a video line is programmable on

the ADV7183. The polarity of HACTIVE is controlled by PHS bit.

3, 14

DVSSIO

Digital I/O Ground

4, 15

DVDDIO

Digital I/O Supply Voltage (3.3 V)

5–8, 19–24,

P15–P0

Video Pixel Output Port. 8-bit multiplexed YCrCb pixel port (P15–P8),

32, 33, 73–76

16-bit YCrCb pixel port (P15–P8 = Y and P7–P0 = Cb,Cr).

9, 31, 71

DVSS1–3

Ground for Digital Supply

10, 30, 72

DVDD1–3

Digital Supply Voltage (3.3 V)

AFF

Almost Full Flag. A FIFO control signal indicating when the FIFO has

reached the almost full margin set by the user (use FFM[4:0]). The polarity

of this signal is controlled by the PFF bit.

HFF/QCLK/GL

I/O

Half Full Flag. A multifunction pin, (OM_SEL[1:0] = 1, 0) is a FIFO

control signal that indicates when the FIFO is half full. The QCLK

(OM_SEL[1:0] = 0, 1) pin function is a qualified pixel output clock when

using FIFO SCAPI mode. The GL (OM_SEL[1:0] = 0, 0) function

(Genlock output) is a signal that contains a serial stream of data that contains

information for locking the subcarrier frequency. The polarity of HFF signal

is controlled by PFF bit.

AEF

Almost Empty Flag. A FIFO control signal, it indicates when the FIFO

has reached the almost empty margin set by the user (use FFM[4:0]). The

polarity of this signal is controlled by PFF bit.

CLKIN

Asynchronous FIFO Clock. This asynchronous clock is used to output

data onto the P19-P0 bus and other control signals.

17, 18, 34, 35

GPO[3:0]

General-Purpose Outputs controlled via I

LLCREF

Clock Reference Output. This is a clock qualifier distributed by the inter-

nal CGC for a data rate of LLC2. The polarity of LLCREF is controlled

by the PLLCREF bit.

LLC2

Line-Locked Clock System Output Clock/2 (13.5 MHz)

LLC1/PCLK

Line-Locked Clock System Output Clock. A dual-function pin (27 MHz

± 5%)

or a FIFO output clock ranging from 20 MHz to 35 MHz.

XTAL1

Second terminal for crystal oscillator; not connected if external clock

source is used.

XTAL

Input terminal for 27 MHz crystal oscillator or connection for external

oscillator with CMOS-compatible square wave clock signal

PWRDN

Power-Down Enable. A logical low will place part in a power-down status.

ELPF

This pin is used for the External Loop Filter that is required for the LLC PLL.

PVDD

PVSS

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