REV. 0

–30–

ADV7183

Table XXXII. Pixel Delay Control Register (Subaddress 27)

Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

RESERVED

0

0

0

Set to Zero

CTA[2:0]

1

0

0

0

Not Valid

0

0

1

Chroma + 2 Pixel (Early)

0

1

0

Chroma + 1 Pixel (Early)

0

1

1

No Delay

1

0

0

Chroma – 1 Pixel (Late)

1

0

1

Chroma – 2 Pixel (Late)

1

1

0

Chroma – 3 Pixel (Late)

1

1

1

Not Valid

RESERVED

1

Set to One

SWPC

2

0

No Swapping

1

Swap the Cr and Cb Values

NOTES

Table XXXIII. Manual Clock Control 1 Register (Subaddress 28)

Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

CLKVAL[17:16]

1

XX

RESERVED

1111

Set to Default

CLKMANE

2

0

Output Frequency Set by Video

1

Frequency Set by CLKVAL[17:0]

FIX27E

3

0

Output Frequency Set by Clock Generator

1

Output 27 MHz Fixed

NOTES

Table XXXIV. Manual Clock Control 2 Register (Subaddress 29)

Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

CLKVAL[15:8]

* XXXXXXXX

*If enabled via CLKMANE, CLKVAL[17:0] determines the fixed output frequency. On the LLC, LLC2, and LLCREF pins.

Table XXXV. Manual Clock Control 3 Register (Subaddress 2A)

Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

CLKVAL[7:0]

*

XXXXXXXX

*If enabled via CLKMANE, CLKVAL[17:0] determines the fixed output frequency. On the LLC, LLC2, and LLCREF pins.