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R5F11BLE Datasheet(PDF) 109 Page - Renesas Technology Corp

Part # R5F11BLE
Description  Ultra-low power consumption technology
PDF  143 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F11BLE Datasheet(HTML) 109 Page - Renesas Technology Corp

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RL78/G1F
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
R01DS0246EJ0110 Rev. 1.10
Page 109 of 140
Aug 12, 2016
Note 1.
Transfer rate in the SNOOZE mode is 4800 bps only.
However, the SNOOZE mode cannot be used when FRQSEL4 = 1.
Note 2.
The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V
≤ EVDD0 < 2.7 V: MAX. 2.6 Mbps
1.8 V
≤ EVDD0 < 2.4 V: MAX. 1.3 Mbps
Note 3.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
32 MHz (2.7 V
≤ VDD ≤ 5.5 V)
16 MHz (2.4 V
≤ VDD ≤ 5.5 V)
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-
pin products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
Remark 1.
Vb [V]: Communication line voltage
Remark 2.
q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1, 5, 7)
Remark 3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11)
Remark 4.
UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is
1.
(5)
Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = -40 to +105°C, 2.4 V
≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V)
(1/2)
Parameter
Symbol
Conditions
HS (high-speed main) mode
Unit
MIN.
MAX.
Transfer rate
reception
4.0 V
≤ EVDD0 ≤ 5.5 V,
2.7 V
≤ Vb ≤ 4.0 V
fMCK/12 Note 1
bps
Theoretical value of the maximum
transfer rate
fMCK = fCLK Note 3
2.6
Mbps
2.7 V
≤ EVDD0 < 4.0 V,
2.3 V
≤ Vb ≤ 2.7 V
fMCK/12 Note 1
bps
Theoretical value of the maximum
transfer rate
fMCK = fCLK Note 3
2.6
Mbps
2.4 V
≤ EVDD0 < 3.3 V,
1.6 V
≤ Vb ≤ 2.0 V
fMCK/12
Notes 1, 2
bps
Theoretical value of the maximum
transfer rate
fMCK = fCLK Note 3
1.3
Mbps



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