R5F11BLE datasheet(113/143 Pages) RENESAS

113 / 143 page

RL78/G1F

3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

R01DS0246EJ0110 Rev. 1.10

Page 113 of 140

Aug 12, 2016

Caution

Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin

products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SOp pin and SCKp pin by using port input

mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with

TTL input buffer selected.

(Remarks are listed two pages after the next page.)

(6)

Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)

(TA = -40 to +105°C, 2.4 V

≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main) mode

Unit

MIN.

MAX.

SCKp cycle time

tKCY1

≥ 4/fCLK

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

600

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

1000

2.4 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

2300

SCKp high-level width

tKH1

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

tKCY1/2 - 150

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

tKCY1/2 - 340

2.4 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

tKCY1/2 - 916

SCKp low-level width

tKL1

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

tKCY1/2 - 24

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

tKCY1/2 - 36

2.4 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

tKCY1/2 - 100

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