R5F564MFDDFB datasheet(178/228 Pages) RENESAS

178 / 228 page

R01DS0173EJ0110 Rev.1.10

Page 178 of 228

Oct 24, 2016

RX64M Group

5. Electrical Characteristics

Note 1. tPBcyc: PCLKB cycle

Figure 5.43

A/D Converter Trigger Input Timing

Note 1. tPBcyc: PCLKB cycle

Note 2. tCAC: CAC count clock source cycle

Table 5.30

A/D Converter Trigger Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

A/D

converter

A/D converter trigger input pulse width

tTRGW

1.5

—

tPBcyc

Figure 5.43

Table 5.31

CAC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

High-drive output is selected by the driving ability control register.

Item*1, *2

Symbol

Min.*1

Max.

Unit*1

Test

Conditions

CAC

CACREF input pulse width

tPBcyc ≤ tcac

tCACREF

4.5 tcac +

3 tPBcyc

—ns

tPBcyc > tcac

5 tcac +

6.5 tPBcyc

—

ADTRG0#,

ADTRG1#

PCLKB

tTRGW

R5F564MFDDFB Datasheet(PDF) 178 Page - Renesas Technology Corp

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