R5F564MFDDFB datasheet(182/228 Pages) RENESAS

182 / 228 page

R01DS0173EJ0110 Rev.1.10

Page 182 of 228

Oct 24, 2016

RX64M Group

5. Electrical Characteristics

Note 1. tPBcyc: PCLKB cycle

Figure 5.46

RSPI Clock Timing and Simple SPI Clock Timing

Table 5.34

Simple SPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

Simple

SPI

SCK clock cycle output (master)

tSPcyc

65536

tPBcyc

Figure 5.46

SCK clock cycle input (slave)

65536

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise/fall time

tSPCKr, tSPCKf

—20

Data input setup time

tSU

33.3

—

Figure 5.47 to

Figure 5.52

Data input hold time

33.3

—

SS input setup time

tLEAD

1—

tSPcyc

SS input hold time

tLAG

1—

tSPcyc

Data output delay time

tOD

—

33.3

Data output hold time

tOH

–10

—

Data rise/fall time

tDr, tDf

—

16.6

SS input rise/fall time

tSSLr, tSSLf

—

16.6

Slave access time

tSA

—5

tPBcyc

Figure 5.51,

Figure 5.52

Slave output release time

tREL

—5

tPBcyc

RSPCKA

master select

output

RSPCKA

slave select input

tSPCKWH

VOH

VOL

VOH

tSPCKWL

tSPCKr

tSPCKf

VOL

tSPcyc

tSPCKWH

VIH

VIL

VIH

tSPCKWL

tSPCKr

tSPCKf

VIL

tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

RSPI

Simple SPI

(n = 0 to 7, 12)

SCKn

master select

output

SCKn

slave select input

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