R5F564MFDDFB datasheet(207/228 Pages) RENESAS

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R01DS0173EJ0110 Rev.1.10

Page 207 of 228

Oct 24, 2016

RX64M Group

5. Electrical Characteristics

5.8

Power-on Reset Circuit and Voltage Detection Circuit Characteristics

Note:

The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1,

and Vdet2 for the POR/ LVD.

Note 1. The low power consumption function is disabled and DEEPCUT[1:0] = 00b or 01b.

Note 2. The low power consumption function is enabled and DEEPCUT[1:0] = 11b.

Note 3. The voltage of VCC = AVCC0 = AVCC1 when LVD1 is enabled must be set to at least 80 mV above the maximum value of the

voltage detection 1 level (Vdet1_1, 2, 3) selected by the LVDLVLR.LVD1LVL[3:0] bits.

Similarly, the voltage of VCC = AVCC0 = AVCC1 when LVD2 is enabled must be set to at least 80 mV above the maximum

value of the voltage detection 2 level (Vdet2_1, 2, 3) selected by the LVDLVLR.LVD2LVL[3:0] bits.

Table 5.50

Power-on Reset Circuit and Voltage Detection Circuit Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

Voltage detection

level

Power-on

reset (POR)

Low power consumption

function disabled*1

VPOR

2.5

2.6

2.7

Figure 5.79

Low power consumption

function enabled*2

2.0

2.35

2.7

Voltage detection circuit (LVD0)

Vdet0_1

2.84

2.94

3.04

Figure 5.80

Vdet0_2

2.77

2.87

2.97

Vdet0_3

2.70

2.80

2.90

Voltage detection circuit (LVD1)

Vdet1_1

2.89

2.99

3.09

Figure 5.81

Vdet1_2

2.82

2.92

3.02

Vdet1_3

2.75

2.85

2.95

Voltage detection circuit (LVD2)

Vdet2_1

2.89

2.99

3.09

Figure 5.82

Vdet2_2

2.82

2.92

3.02

Vdet2_3

2.75

2.85

2.95

Internal reset time

Power-on reset time

tPOR

—

4.6

—

Figure 5.79

LVD0 reset time

tLVD0

—

0.70

—

Figure 5.80

LVD1 reset time

tLVD1

—

0.57

—

Figure 5.81

LVD2 reset time

tLVD2

—

0.57

—

Figure 5.82

Minimum VCC down time

tVOFF

200

—

μs

Figure 5.79,

Figure 5.80

Response delay time

tdet

—

200

μs

Figure 5.79 to

Figure 5.82

LVD operation stabilization time (after LVD is enabled)*3

Td(E-A)

——

μs

Figure 5.81,

Figure 5.82

Hysteresis width (LVD1 and LVD2)

V LVH

—80

—

R5F564MFDDFB Datasheet(PDF) 207 Page - Renesas Technology Corp

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