WM8235 datasheet(19/154 Pages) CIRRUS

19 / 154 page

WM8235

Rev 4.6

CDS/NON-CDS PROCESSING

For CCD type input signals, containing a fixed reference/reset level, the signal may be processed

using Correlated Double Sampling (CDS), which will remove pixel-by-pixel common mode noise. With

CDS processing, the input waveform is sampled at two different points in time for each pixel, once

during the reference/reset level and once during the video level. To sample using CDS, register bit

CDS must be set to 1 (default = 0). This causes the signal reference to come from the video reference

level as shown in Figure 13.

For input signals that do not contain a reference/reset level (e.g. CIS sensor signals), non-CDS

processing is used (CDS=0). In this case, the video level is processed with respect to the voltage on

pin VRLC/VBIAS. The VRLC/VBIAS voltage is sampled during VSMP low period in this mode. Note

that if the A.C. coupling capacitor (CIN) is used in non-CDS mode (CDS=0), then to minimise code

drift, line clamping should be used and internal input voltage buffers enabled using the SF_INP and

SF_VRLC registers. Alternatively, if the input signal contains a stable reference/reset level, then pixel

clamping should be used, and the voltage buffers need not be enabled.

CONTROL

INTERFACE

CIN

IN*

VRLC/

VBIAS

VRLCEN

5-BIT

RLCDAC

VRLC_VSEL[4:0]

RLC switch

VSMP

'Video'

sample

capacitor

'Reference'

sample

capacitor

VSMP

CLAMP

VSMP (if CDS=0)

RSMP (if CDS=1)

VSMP (if CDS=0)

Figure 13 CDS/non-CDS Input Configuration

WM8235 Datasheet(PDF) 19 Page - Cirrus Logic