HC705J2 datasheet(34/78 Pages) MOTOROLA

34 / 78 page

MC68HC705J2

CENTRAL PROCESSOR UNIT

MOTOROLA

4-15

Bit test and branch instructions cause a branch based on the condition of any

readable bit in the first 256 memory locations. These three-byte instructions use

a combination of direct addressing and relative addressing. The direct address

of the byte to be tested is in the byte following the opcode. The third byte is the

signed offset byte. The CPU finds the conditional branch destination by adding

the third byte to the program counter if the specified bit tests true. The bit to be

tested and its condition (set or clear) is part of the opcode.

The span of

branching is from –128 to +127 from the address of the next location after the

branch instruction. The CPU also transfers the tested bit to the carry/borrow bit

of the condition code register. Table 4-9 lists the jump and branch instructions.

Table 4-9. Jump and Branch Instructions

Instruction

Mnemonic

Branch Always

BRA

Branch Never

BRN

Branch if Bit n of M = 0

BRCLR

Branch if Bit n of M = 1

BRSET

Branch if Higher

BHI

Branch if Lower or Same

BLS

Branch if Carry Clear

BCC

Branch if Higher or Same

BHS

Branch if Carry Set

BCS

Branch if Lower

BLO

Branch if Not Equal

BND

Branch if Equal

BEQ

Branch if Half-Carry Clear

BHCC

Branch if Half-Carry Set

BHCS

Branch if Plus

BPL

Branch if Minus

BMI

Branch if Interrupt Mask Clear

BMC

Branch if Interrupt Mask Set

BMS

Branch if Interrupt Line Low

BIL

Branch if Interrupt Line High

BIH

Branch to Subroutine

BSR

Jump Unconditional

JMP

Jump to Subroutine

JSR

HC705J2 Datasheet(PDF) 34 Page - Motorola, Inc

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