HC705J2 datasheet(22/78 Pages) MOTOROLA

22 / 78 page

MC68HC705J2

CENTRAL PROCESSOR UNIT

MOTOROLA

4-3

4.1.4 Program Counter

The program counter is a 16-bit register that contains the address of the next

instruction or operand to be fetched.

The four most significant bits of the

program counter are permanently fixed at 0000. In MC68HC05J1 emulation

mode, the five most significant bits are fixed at 00000.

Normally, the address in the program counter automatically increments to the

next sequential memory location every time an instruction or operand is fetched.

Jump, branch, and interrupt operations load the program counter with an

address other than that of the next sequential location.

4.1.5 Condition Code Register

The condition code register is an 8-bit register whose three most significant bits

are permanently fixed at 111. The condition code register contains the interrupt

mask and four flags that indicate the results of the instruction just executed. The

following paragraphs describe the functions of the condition code register.

4.1.5.1 Half-Carry Flag

The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of

the accumulator during an ADD or ADC operation.

The half-carry flag is

required for binary-coded decimal (BCD) arithmetic operations.

4.1.5.2 Interrupt Mask

Setting the interrupt mask disables interrupts.

If an interrupt request occurs

while the interrupt mask is zero, the CPU saves the CPU registers on the stack,

sets the interrupt mask, and then fetches the interrupt vector.

If an interrupt

request occurs while the interrupt mask is set, the interrupt request is latched.

Normally, the CPU processes the latched interrupt as soon as the interrupt

mask is cleared again.

A return from interrupt (RTI) instruction pulls the CPU registers from the stack,

restoring the interrupt mask to its cleared state. After any reset, the interrupt

mask is set and can be cleared only by a software instruction.

HC705J2 Datasheet(PDF) 22 Page - Motorola, Inc