XRT4500CV datasheet(4/99 Pages) EXAR

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XRT4500

MULTIPROTOCOL SERIAL NETWORK INTERFACE IC

REV. 1.0.7

TABLE OF CONTENTS

GENERAL DESCRIPTION................................................................................................. 1

Block Diagram........................................................................................................................................... 1

FEATURES...................................................................................................................................... 1

APPLICATIONS ................................................................................................................................1

Block Diagram........................................................................................................................................... 2

Pin Out of the Device ................................................................................................................................ 3

Ordering Information ................................................................................................................................. 3

TABLE OF CONTENTS ............................................................................................................ I

PIN DESCRIPTIONS .......................................................................................................... 4

ELECTRICAL CHARACTERISTICS .................................................................................................... 26

TA = 25°C, VDD = 5V, VSS = -6V, VPP = 12V, Maximum Operating Frequency Unless Otherwise Specified

Power Supply Consumption.................................................................................................................... 29

FIGURE 1. SUPPLY CURRENT VERSUS TEMPERATURE AND SUPPLY VOLTAGE, WITHOUT LOAD OR SIGNAL IN EIA-530 (V.11)

MODE

......................................................................................................................................................... 29

FIGURE 2. SUPPLY CURRENT VERSUS TEMPERATURE AND SUPPLY VOLTAGE, WITH LOAD IN EIA-530 (V.11) MODE ... 30

FIGURE 3. RS422 DRIVER TEST CIRCUIT ................................................................................................................. 33

FIGURE 4. RS422 DRIVER/RECEIVER AC TEST CIRCUIT........................................................................................... 33

FIGURE 5. V.35 DRIVER/RECEIVER AC TEST CIRCUIT (TX1/RX1, TX2/RX2 ONLY) .................................................. 34

FIGURE 6. V.10/V.28 DRIVER TEST CIRCUIT ............................................................................................................ 34

FIGURE 7. V.10 (RS-423) V.28 (RS-232) RECEIVER TEST CIRCUIT ......................................................................... 34

FIGURE 8. V.11, V.35 DRIVER PROPAGATION DELAYS.............................................................................................. 34

FIGURE 9. V.11, V.35 RECEIVER PROPAGATION DELAYS.......................................................................................... 34

FIGURE 10. V.10 (RS-423) V.28 (RS-232) DRIVER PROPAGATION DELAYS ............................................................. 35

FIGURE 11. V.10, V.28 RECEIVER PROPAGATION DELAYS........................................................................................ 35

TABLE 1: RECEIVER SPECIFICATIONS ....................................................................................................................... 35

TABLE 2: TRANSMITTER SPECIFICATION.................................................................................................................... 36

1.0 SYSTEM DESCRIPTION ..................................................................................................................... 37

1.1 THE DIFFERENCE BETWEEN AN ELECTRICAL INTERFACE AND A COMMUNICATIONS INTERFACE 37

TABLE 3: DTE MODE - CONTROL PROGRAMMING FOR DRIVER AND RECEIVER MODE SELECTION .............................. 38

TABLE 4: DCE MODE - CONTROL PROGRAMMING FOR DRIVER AND RECEIVER MODE SELECTION.............................. 38

1.2 THE SYSTEM ARCHITECTURE .................................................................................................................... 39

1.2.1 THE “HIGH -SPEED TRANSCEIVER” BLOCK ......................................................................................................... 40

FIGURE 12. HIGH-SPEED TRANSCEIVER BLOCK ........................................................................................................ 40

1.2.2 THE “HANDSHAKING/CONTROL SIGNAL TRANSCEIVER” BLOCK .................................................................... 41

FIGURE 13. HANDSHAKING/CONTROL TRANSCEIVER BLOCK ...................................................................................... 41

1.2.3 THE “DIAGNOSTIC OPERATION INDICATOR TRANSCEIVER” BLOCK............................................................... 42

FIGURE 14. DIAGNOSTIC OPERATION INDICATOR TRANSCEIVER BLOCK ..................................................................... 42

1.3 THE CONTROL BLOCK ................................................................................................................................. 43

FIGURE 15. DIAGRAM OF THE XRT4500 CONTROL BLOCK........................................................................................ 43

1.3.1 M[2:0] - THE (COMMUNICATION INTERFACE) MODE CONTROL SELECT PINS. ............................................... 44

TABLE 5: THE RELATIONSHIP BETWEEN THE SETTINGS FOR THE M[2:0] BIT-FIELDS AND THE CORRESPONDING COMMUNICA-

TION

INTERFACE THAT IS SUPPORTED.......................................................................................................... 44

1.3.2 DCE/DTE - THE DCE/DTE MODE SELECT PIN ........................................................................................................ 45

FIGURE 16. A SIMPLE ILLUSTRATION OF THE DCE/DTE INTERFACE .......................................................................... 45

1.3.3 THE LP - LOOP-BACK ENABLE/DISABLE SELECT PIN ........................................................................................ 46

FIGURE 17. ILLUSTRATION OF BOTH THE DTE AND DCE MODE XRT4500 OPERATING, WHEN THE LOOP-BACK MODE IS DIS-

ABLED

........................................................................................................................................................ 46

FIGURE 18. ILLUSTRATION OF THE BEHAVIOR THE DTE MODE XRT4500, WHEN IT IS CONFIGURED TO OPERATE IN THE LOOP-

BACK MODE............................................................................................................................................... 47

FIGURE 19. ILLUSTRATION OF THE BEHAVIOR OF THE DCE MODE XRT4500, WHEN IT IS CONFIGURED TO OPERATE IN THE

LOOP-BACK MODE...................................................................................................................................... 48

1.3.4 THE EC* (ECHO CLOCK MODE - ENABLE/DISABLE SELECT INPUT PIN) .......................................................... 49

FIGURE 20. ILLUSTRATION OF A TYPICAL “3-CLOCK DCE/DTE” INTERFACE ............................................................... 49

FIGURE 21. ILLUSTRATION OF THE WAVE-FORMS OF THE SIGNALS THAT ARE TRANSPORTED ACROSS A “3-CLOCK DTE/DCE”

INTERFACE................................................................................................................................................. 50

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