LPC47M182 datasheet(10/223 Pages) SMSC

10 / 223 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

SMSC LPC47M182

DATASHEET

Table 7.47 – Latched Backfeed Cut Sequence 1 and 2 Timing .................................................................................150

Table 7.48 – nRSMRST Pin.......................................................................................................................................152

Table 7.49 – CNR Pins ..............................................................................................................................................152

Table 7.50 – CNR Logic Truth Table..........................................................................................................................153

Table 8.1 – Power Control Runtime Registers Summary, LD_NUM Bit = 0 ...............................................................154

Table 8.2 – Power Control Runtime Registers Description, LD_NUM Bit = 0 ............................................................155

Table 9.1 – GPIO Runtime Registers Summary, LD_NUM = 0..................................................................................161

Table 9.2 – GPIO Runtime Registers Description, LD_NUM = 0 ...............................................................................162

Table 10.1 – Runtime Register Block Runtime Registers Summary ..........................................................................165

Table 11.1– LPC47M182 Configuration Registers Summary, LD_NUM bit = 0 .........................................................170

Table 11.2 – LPC47M182 Configuration Register Summary, LD_NUM bit = 1 .........................................................172

Table 11.3 – Chip Level Registers .............................................................................................................................174

Table 11.4 – Logical Device Registers.......................................................................................................................177

Table 11.5 – Primary Interrupt Select Configuration Register Description .................................................................179

Table 11.6 – DMA Channel Select Configuration Register Description......................................................................179

Table 11.7 – Logical Device I/O Address, LD_NUM Bit = 0 ......................................................................................181

Table 11.8 – Logical Device I/O Address, LD_NUM Bit = 1 .......................................................................................182

Table 11.9 – Floppy Disk Controller Logical Device Configuration Registers ............................................................184

Table 11.10 – Serial Port 2 Logical Device Configuration Registers ..........................................................................187

Table 11.11 – Parallel Port Logical Device Configuration Registers ..........................................................................188

Table 11.12 – Serial Port 1 Logical Device Configuration Registers ..........................................................................189

Table 11.13 – Keyboard Logical Device Configuration Registers ..............................................................................190

Table 11.14 – Power Control/Runtime Register Block Logical Device Configuration Registers.................................191

Table 12.1 – Operational DC Characteristics.............................................................................................................192

Table 12.2 – S3-S5 Standby Current .........................................................................................................................197

Table 13.1 – nIDE_RSTDRV Timing..........................................................................................................................217

Table 13.2 – nPCIRST_OUT and nPCIRST_OUT2 Timing .......................................................................................217

Table 13.3 – PS_ON Timing ......................................................................................................................................217

Table 13.4 – SCK_BJT_GATE Timing .......................................................................................................................218

Table 13.5 – PWRGD_PLATFORM Timing ...............................................................................................................218

Table 13.6 – CNR CODEC Down Enable Timing.......................................................................................................218

Table 13.7 – Resume Reset Timing...........................................................................................................................219

Table 14.1 – 128 Pin QFP Package Parameters .......................................................................................................220

Table 15.1 – XOR Test Pattern Example ...................................................................................................................222

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