AD9925BBCZRL datasheet(55/96 Pages) AD

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AD9925

Rev. A | Page 55 of 96

STANDBY MODE OPERATION

The AD9925 contains three different standby modes to optimize

the overall power dissipation in a particular application. Bits [1:0]

of the OPRMODE register control the power-down state of the

device:

OPRMODE[1:0] = 00 = Normal Operation (Full Power)

OPRMODE[1:0] = 01 = Standby 1 Mode

OPRMODE[1:0] = 10 = Standby 2 Mode

OPRMODE[1:0] = 11 = Standby 3 Mode (Lowest Overall Power)

Table 34 and Table 35 summarize the operation of each power-

down mode. Note that the OUT_CONTROL register takes

priority over the standby 1 and standby 2 modes in determining

the digital output states, but the standby 3 mode takes priority

over OUT_CONTROL. Standby 3 mode has the lowest power

consumption and even shuts down the crystal oscillator circuit

between CLI and CLO. Thus, if CLI and CLO are being used

with a crystal to generate the master clock, this circuit will be

powered down and there will be no clock signal. When return-

ing from standby 3 mode to normal operation, the timing core

must be reset at least 500 µs after the OPRMODE register is

written to. This will allow sufficient time for the crystal circuit

to settle.

The XV and shutter outputs can also be programmed to hold a

specific value during any of the standby modes, as detailed in

Table 35.

Table 34. Standby Mode Operation

I/O Block

Standby 3 (Default)1, 2

OUT_CONT= LO2

Standby 23, 4

Standby 13, 4

AFE

Off

No Change

Off

Timing Core

Off

No Change

Off

CLO Oscillator

Off

No Change

CLO

High

Running

Hi-Z

Low

Low (4.3 mA)

Hi-Z

High

High (4.3 mA)

Hi-Z

Low

Low (4.3 mA)

Hi-Z

High

High (4.3 mA)

Hi-Z

Low

Low (4.3 mA)

Low

VDHDPOL Value

Undefined in Master Mode

Low

VDHDPOL Value

Undefined in Master Mode

DCLK

Low

Running if DCLK MODE =1

DOUT

Low

1 To exit standby 3 mode, first write a 00 to OPRMODE[1:0], then reset the timing core after ~500 µs to guarantee proper settling of the oscillator.

2 Standby 3 mode takes priority over OUT_CONTROL for determining the output polarities.

3 These polarities assume OUT_CONT = High., because OUT_CONTROL = Low takes priority over standby 1 and standby 2 modes.

4 Standby 1 and standby 2 modes will set H and RG drive strength to minimum value (4.3 mA).

AD9925BBCZRL Datasheet(PDF) 55 Page - Analog Devices

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