SLG46721 datasheet(47/101 Pages) DIALOG

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SLG46721

10.3 3-Bit LUT or Pipe Delay Macrocell

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay.

When used to implement LUT functions, the 3-bit LUT take in three input signals from the connection matrix and produces a single

output, which goes back into the connection matrix.

When used as a pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK) and Reset (RST). The pipe

delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF

cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell. The first delay option (OUT2) is fixed at

the output of the first flip-flop stage. The other two outputs (OUT0 and OUT1) provide user selectable options for 1 – 16 stages

of delay There are delay output points for each set of the OUT0 and OUT1 outputs to a 4-input mux that is controlled by reg

<666:663> for OUT0 and reg <670:667> for OUT1. The 4-input mux is used to control the selection of the amount of delay.

The overall time of the delay is based on the clock used in the SLG46721 design. Each DFF cell has a time delay of the inverse

of the clock time (either external clock or the RC Oscillator within the SLG46721). The sum of the number of DFF cells used will

be the total time delay of the Pipe Delay logic cell.

Figure 15. 3-bit LUT8 or Pipe Delay

3-bit LUT8 OUT

IN1

IN0

reg <670:663>

From Connection

Matrix Output <59>

From Connection

Matrix Output <60>

IN2

From Connection

Matrix Output <61>

16 Flip-Flops

RST

CLK

From Connection

Matrix Output <60>

From Connection

Matrix Output <59>

From Connection

Matrix Output <61>

reg <670:667>

reg <666:663>

To Connection

Matrix Input<41>

To Connection

Matrix Input <40>

OUT1

OUT0

reg <964>

To Connection

Matrix Input <34>

OUT2

reg <963>

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