SLG46721 datasheet(78/101 Pages) DIALOG

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SLG46721

18.0 RC Oscillator (RC Osc)

18.1 RC Oscillator Overview

The SLG46721 has two internal RC oscillators, one that runs at 25 kHz and one that runs at 2 MHz. The user can select one of

these fundamental frequencies for the RC OSC Macrocell, or the fundamental frequency can also come from an external clock

input (Pin 20). There are two divider stages that allow the user flexibility for introducing clock signals on various Connection Matrix

Input lines. The first stage divider allows the selection of /1, /2, /4 or /8 divide down frequency from the fundamental. The second

stage divider has an input of one frequency from the first stage divider, and outputs five different frequencies on Connection Matrix

Input lines <45>, <46>, <47>, <48>, and <49>. See Figure 40 below for details of the frequencies for each of these five Connection

Matrix Inputs.

If PWR DOWN input of oscillator is LOW, the oscillator will be turned on. If PWR DOWN input of oscillator is HIGH the oscillator

will be turned off. The PWR DOWN signal has the highest priority.

18.2 RC OSC Block Diagram

Figure 40. RC OSC Block Diagram

Internal RCO

reg <708>

0: 25 kHz

1: 2 MHz

Pin 20 Ext. Clock

Ext. Clk Sel reg <712>

/ 4

/ 8

/ 12

/ 24

/ 64

/ 3

To Connection Matrix Input <45>

To Connection Matrix Input <46>

To Connection Matrix Input <49>

To Connection Matrix Input <48>

To Connection Matrix Input <47>

reg <711:710>

DIV /1/2/4/8

reg <566:565>

First Stage

Divider

Second Stage

Divider

From Connection Matrix Output <75>

PWR DOWN

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