| Electronic Components Datasheet Search |
|
SLG46721 Datasheet(PDF) 80 Page - Dialog Semiconductor |
|
|
|||||||||||||||||||||||||||||
SLG46721 Datasheet(HTML) 80 Page - Dialog Semiconductor |
|
80 / 101 page ![]() 000-0046721-114 Page 79 of 100 SLG46721 19.2.2 Power Down During powerdown, macrocells in SLG46721 are powered off and logic macrocells may switch states after falling below 1.4 V. The I/O buffers are disabled when POR goes low at VDD~1 V. Please note that during a slow rampdown, outputs can possibly switch state during this time. Figure 42. Power Down Outputs can possibly switch state during this time VDD (V) Time 1.6 V 1.15 V 2 V 1 V 1 V VREF Out Signal |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |