SLG46721 datasheet(34/101 Pages) DIALOG

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000-0046721-114

Page 33 of 100

SLG46721

8.2

Matrix Output Table

Table 25. Matrix Output Table

Address

Matrix Output Signal Function

Matrix Output

Number

reg<5:0>

Matrix Out: PIN3 Digital Output Source

reg<11:6>

Matrix Out: Output Enable of PIN3

reg<17:12>

Matrix Out: PIN4 Digital Output Source

reg<23:18>

Matrix Out: PIN5 Digital Output Source

reg<29:24>

Matrix Out: Output Enable of PIN5

reg<35:30>

Matrix Out: PIN6 Digital Output Source

reg<41:36>

Matrix Out: PIN7 Digital Output Source

reg<47:42>

Matrix Out: Output Enable of PIN7

reg<53:48>

Matrix Out: PIN8 Digital Output Source

reg<59:54>

Matrix Out: PIN9 Digital Output Source

reg<65:60>

Matrix Out: Output Enable of PIN9

reg<71:66>

Matrix Out: PIN10 Digital Output Source (Super Drive)

reg<77:72>

Matrix Out: pdb (power down) for ACMP0

reg<83:78>

Matrix Out: pdb (power down) for ACMP1

reg<89:84>

Matrix Out: pdb (power down) for ACMP2

reg<95:90>

Matrix Out: Input for delay0 or Counter0 external clock

reg<101:96>

Matrix Out: Input for delay1 or counter1 reset input

reg<107:102>

Matrix Out: Input for Counter1 external clock or delay1 external clock

reg<113:108>

Matrix Out: Input for delay4 or Counter4 external clock

reg<119:114>

Matrix Out: Input for delay5 or Counter5 external clock

reg<125:120>

Matrix Out: Input for delay6 or Counter6 external clock

reg<131:126>

Matrix Out: Input for filter_0

reg<137:132>

Matrix Out: Input for filter_1

reg<143:138>

Matrix Out: pdb (power down) for ACMP3

reg<149:144>

Matrix Out: In0 of LUT3_9

reg<155:150>

Matrix Out: In1 of LUT3_9

reg<161:156>

Matrix Out: In2 of LUT3_9

reg<167:162>

Matrix Out: In0 of LUT4_0 or Input for Counter2 (delay2) external clock

reg<173:168>

Matrix Out: In1 of LUT4_0 or Input for delay2 (counter2 reset input)

reg<179:174>

Matrix Out: In2 of LUT4_0

reg<185:180>

Matrix Out: In3 of LUT4_0

reg<191:186>

Matrix Out: In0 of LUT4_1 or Input for Counter3(delay3) external clock

reg<197:192>

Matrix Out: In1 of LUT4_1 or Input for delay3(counter3 reset input)

reg<203:198>

Matrix Out: In2 of LUT4_1

reg<209:204>

Matrix Out: In3 of LUT4_1

reg<215:210>

Matrix Out: In0 of LUT3_0

reg<221:216>

Matrix Out: In1 of LUT3_0

reg<227:222>

Matrix Out: In2 of LUT3_0

SLG46721 Datasheet(PDF) 34 Page - Dialog Semiconductor

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