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SLG46721 Datasheet(PDF) 1 Page - Dialog Semiconductor |
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SLG46721 Datasheet(HTML) 1 Page - Dialog Semiconductor |
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1 / 101 page  Silego Technology, Inc. Rev 1.14 000-0046721-114 Revised December 5, 2017 GreenPAK Programmable Mixed Signal Array SLG46721 Block Diagram Features • Logic & Mixed Signal Circuits • Highly Versatile Macrocells • Read Back Protection (Read Lock) • 1.8 V (±5%) to 5 V (±10%) Supply • Operating Temperature Range: -40°C to 85°C • RoHS Compliant / Halogen-Free • 20-pin STQFN: 2 x 3 x 0.55 mm, 0.4 mm pitch Applications • Personal Computers and Servers • PC Peripherals • Consumer Electronics • Data Communications Equipment • Handheld and Portable Electronics Pin Configuration GPIO GPIO GPIO GPIO GPIO GPIO 2 3 414 15 16 17 GPI VDD 1 STQFN-20 (Top View) GPIO GPIO 5 6 GPIO GPIO 12 13 GPIO 7 GND 11 8 9 10 18 19 20 3-bit LUT3_8 or Pipe Delay Pin 6 GPIO Vref Programmable Delay RC Oscillator Pin 7 GPIO Pin 1 VDD Pin 2 GPI Pin 3 GPIO Pin 4 GPIO Pin 5 GPIO Pin 20 GPIO Pin 19 GPIO Pin 18 GPIO Pin 8 GPIO Pin 9 GPIO Pin 10 GPIO Pin 12 GPIO Pin 11 GND Pin 17 GPIO Pin 16 GPIO Pin 15 GPIO Pin 14 GPIO Pin 13 GPIO INV_0 ACMP0 ACMP1 ACMP2 ACMP3 FILTER_0 INV_1 Additional Logic Functions Look Up Tables (LUTs) Counters/Delay Generators CNT0 CNT4 CNT1 CNT5 CNT6 2-bit LUT2_4 3-bit LUT3_0 2-bit LUT2_5 3-bit LUT3_1 3-bit LUT3_5 3-bit LUT3_4 3-bit LUT3_6 3-bit LUT3_9 3-bit LUT3_7 Combination Function Macrocells 2-bit LUT2_0 or DFF4 2-bit LUT2_2 or DFF6 2-bit LUT2_1 or DFF5 2-bit LUT2_3 or DFF7 3-bit LUT3_3 or DFF3 3bit LUT3_2 or DFF2 4-bit LUT4_1 or CNT3 4-bit LUT4_0 or CNT2 FILTER_1 POR |
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