CS43L36 datasheet(59/89 Pages) CIRRUS

59 / 89 page

DS1081F3

CS43L36

6.15 ID Registers

7 Register Descriptions

The tables in this section give bit assignments, definitions, and default states after power-up or reset. Reserved register

fields must maintain default states. Section 6 describes the red, turquoise, and orange indicators.

7.1 Global Registers

0x08–0x7F Reserved

—

xxxx

I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94(Write); 10010(AD1)(AD0)1 = 0x95 (Read)

Page 0x30—ID Registers

Address

Function

765

43210

0x00

Control Port Page

PAGE

001

10000

0x01–0x13 Reserved

—

xxxxx

xxx

0x14

Subrevision

SUBREVISION

p. 80

xxxxx

xxx

0x15

Device ID A and B

(Read Only)

DEVIDA

DEVIDB

p. 80

010

00011

0x16

Device ID C and D

(Read Only)

DEVIDC

DEVIDD

p. 80

101

00011

0x17

Device ID E (Read

Only)

DEVIDE

—

p. 80

011

0x–0x7F

Reserved

—

xxxxx

xxx

7.1.1

Revision ID

Address 0x1005

R/O

76543210

AREVID

MTLREVID

Default

xxxxxxxx

Bits

Name

Description

7:4

AREVID

Alpha revision. CS43L36 alpha revision level. AREVID and MTLREVID form the complete device revision ID (e.g.,: A0, B2).

0x00 … 0xFF

3:0 MTLREVID Metal revision. CS43L36 metal revision level. AREVID and MTLREVID form the complete device revision ID (e.g.,: A0, B2).

0x00 … 0xFF

7.1.2

Freeze Control

Address 0x1006

R/W

7654321

—

FREEZE

Default

000000

Bits

Name

Description

7:1

—

Reserved

FREEZE Freeze registers. Configures a hold on all volume-control and power-down register settings. Use this bit only during normal

operation after all circuit blocks in use have powered up. Using the bit when an affected circuit block is powering up could cause

the change to occur immediately when power up completes (i.e., not gated by the FREEZE bit). Bits affected by FREEZE are

shown in orange throughout Section 6 and Section 7.

0 (Default) Volume-control and power-down register changes take effect immediately.

1 Modifications made to volume-control and power-down registers take effect only after this bit is cleared.

I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)

Page 0x2A—Serial Port Receive Registers

Address

Function

543210

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