CS43L36 datasheet(62/89 Pages) CIRRUS

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DS1081F3

CS43L36

7.2 Power Down and Headset Detects

2:0

ACC_

TO_SEL

APB access timeout select. Determines the timeout duration in MCLKs.

000 7 MCLKs

001 15 MCLKs

010 31 MCLKs

011 63 MCLKs

100 127 MCLKs

101 255 MCLKs

110 511 MCLKs

111 (Default) 65,535 MCLKs

7.2.1

Power Down Control 1

Address 0x1101

R/W

765

43210

—

ASP_DAI_PDN

MIXER_PDN

—

HP_PDN

—

PDN_ALL

Default

111111

Bits

Name

Description

7—

Reserved

ASP_

DAI_

PDN

ASP DAI0 input path power down. Configures ASP DAI0 SDIN path power state.

0 Powered up

1 (Default) Powered down. Setting this bit does not tristate the serial port clock.

MIXER_

PDN

Mixer power down. Configures the mixer power state.

0 The mixer is powered up.

1 (Default) The mixer is powered down.

4—

Reserved

HP_

PDN

HPOUTx power down

0 The HP driver and DACx are powered up.

1 (Default) The HP driver and DACx are powered down.

2:1

—

Reserved

PDN_

ALL

DAC power down. Configures the entire DAC’s power state except for PLL_START. After power up (PDN_ALL: 1

 0),

individual subblocks are powered according to power-control programming. This bit is affected by LATCH_TO_VP (see p. 74).

Note: The SRC power-down state depends on the SRC_PDN_OVERRIDE setting (see p. 62).

0 Powered up, per the individual x_PDN controls

1 (Default) Powered down. PDN_ALL must not be set without first enabling LATCH_TO_VP. After PDN_ALL is set and the

entire DAC is powered down, PDN_DONE is set, indicating that SCLK can be removed.

7.2.2

Power Down Control 2

Address 0x1102

R/W

765

43210

—

DISCHARGE_

FILT+

SRC_PDN_

OVERRIDE

—

DAC_SRC_

PDNB

—

Default

000100

Bits

Name

Description

7:5

—

Reserved

DISCHARGE_

FILT+

Discharge FILT+ capacitor. Configures the state of the FILT+ pin internal clamp. Before setting this bit, ensure that the

VD_FILT device input is connected to a supply, as shown in Table 3-2.

0 (Default) FILT+ is not clamped to ground.

1 FILT+ is clamped to ground. This must be set only if PDN_ALL = 1. Discharge time with an external 2.2-µF

capacitor on FILT+ is ~46 ms.

SRC_PDN_

OVERRIDE

SRC power down override. Configures the SRCs’ power states.

0 (Default) Power state control for the DAC SRCs, which are controlled by the following smart logic:

• DAC SRCs are off if SRC_BYPASS_DAC = 1.

• • If PDN_ALL = 1, all SRCs are off.

• If PDN_ALL = 0 and the respective DAC bypass bits = 0, the following controls each SRC’s power state:

–If DAI0 is enabled, the DAC SRCs are powered up.

1 DAC SRCs are controlled by DAC_SRC_PDNB.

2—

Reserved

DAC_SRC_

PDNB

DAC SRC power down. Configures the DAC ASP power state if SRC_PDN_OVERRIDE = 1.

0 (Default) Power down

1 Power up audio DAC SRC only

0—

Reserved

Bits Name

Description

CS43L36 Datasheet(PDF) 62 Page - Cirrus Logic

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