CS43L36 datasheet(17/89 Pages) CIRRUS

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DS1081F3

CS43L36

3 Characteristics and Specifications

Table 3-12. Digital Audio Interface Timing Characteristics

Test conditions (unless specified otherwise): GNDA = GNDL = GNDCP = 0 V; all voltages with respect to ground; values are for both VL = 1.2 and 1.8 V;

inputs: Logic 0 = GNDL = 0 V, Logic 1 = VL; TA = +25°C; CLOAD = 30 pF (for VL = 1.2 V) and 60 pF (for VL = 1.8 V); input timings are measured at VIL

and VIH thresholds; output timings are measured at VOL and VOH thresholds (see Table 3-14); ASP_TX_HIZ_DLY = 00.

Parameters 12,3

1.Output clock frequencies follow SCLK frequency proportionally. Deviation of the bit-clock source from nominal supported rates is directly imparted to

the output clock rate by the same factor (e.g., +100-ppm offset in the frequency of SCLK becomes a +100-ppm offset in MCLK and LRCK).

2.I2S interface timing

3.TDM interface timing

Symbol

Minimum Typical Maximum Unit

ASP_SCLK frequency 4

4.SCLK is mastered from an external device. The external device is expected to maintain SCLK timing specifications.

fSCLK

0.973 [5]

5.SCLK operation below 2.8224 MHz may result in degraded performance.

—25.81

MHz

SCLK high period 4

tHI:SCLK

18.5

—

SCLK low period 4

tLO:SCLK

18.5

—

SCLK duty cycle 4

—45

—

Hybrid-

Master

Mode

FSYNC/LRCK frame rate

—

0.99

—

1.01

LRCK duty cycle

—

FSYNC high period 6

6.Maximum LRCK duty cycle is equal to frame length, in SCLK periods, minus 1. Maximum duty cycle occurs when LRCK_HI is set to 511 SCLK

periods and LRCK period is set to 512 SCLK periods.

tHI:FSYNC

1/fSCLK

—

(n–1)/fSCLK

FSYNC/LRCK delay time after SCLK launching edge 7

7.Data is latched on the rising or falling edge of SCLK, as determined by ASP_SCPOL_IN_x and ASP_FSD (See Section 7.3.6 and Section 7.3.7).

VL = 1.8 V

VL = 1.2 V

tD:CLK–LRCK

—

SDIN setup time before SCLK latching edge 7

tSU:SDI

—

SDIN hold time after SCLK latching edge 7

tH:SDI

5—

—

Slave

Mode

FSYNC/LRCK frame rate

—

0.99

—

1.01

FSYNC/LRCK duty cycle

—

FSYNC/LRCK setup time before SCLK latching edge 7

tSU:LRCK

—

FSYNC/LRCK hold time after SCLK latching edge 7

tH:LRCK

5—

—

SDIN hold time after SCLK latching edge 7

tH:SDI

5—

—

FSYNC/LRCK duty cycle

—

Table 3-13. I2C Slave Port Characteristics

Test conditions (unless specified otherwise): Fig. 2-1 shows typical connections; Inputs: GNDA = GNDL = GNDCP = 0 V; all voltages with respect to

ground; min/max performance data taken with VL = 1.66–1.94 V (VL_SEL = VP) or VL = 1.1–1.3 V (VL_SEL = GNDD); inputs: Logic 0 = GNDA = 0 V,

Logic 1 = VL; TA = +25°C; SDA load capacitance equal to maximum value of CB = 400 pF; minimum SDA pull-up resistance, RP(min).1 Table 3-1

describes some parameters in detail. All specifications are valid for the signals at the pins of the CS43L36 with the specified load capacitance.

Parameter 2

Symbol 3

Minimum

Maximum

Unit

SCL clock frequency

fSCL

—1000

kHz

Clock low time

tLOW

500

—

Clock high time

tHIGH

260

—

Start condition hold time (before first clock pulse)

tHDST

260

—

Setup time for repeated start

tSUST

260

—

Rise time of SCL and SDA

Standard Mode

Fast Mode

Fast Mode Plus

tRC

—

1000

300

120

SCLK

SDIN

tSU:SDI

tH:SDI

LRCK

1/fSCLK

tSU:LRCLK

tD:CLK‐LRCLK

tH:LRCLK

tHI:SCLK

tLO:SCLK

SCLK

SDIN

tSU:SDI

tH:SDI

LRCK/FSYNC

tD:CLK-FSYNC

1/fSCLK

Don’t Care

Frame location 0

Frame location N-1

1/Fs

...

fSCLK = N ∙ Fs

tSU:FSYNC

tH:FSYNC

tHI:FSYNC

tLO:SCLK

tHI:SCLK

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