TLE9255WLC datasheet(47/100 Pages) INFINEON

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Data Sheet

Rev. 1.02 2018-02-02

TLE9255W

Serial Peripheral Interface

The communication between the microcontroller and the transceiver is implemented via Serial Peripheral

Interface (SPI). This communication is configured as a full duplex multi slave data transfer. A valid SPI

command consists of 16 bits.

Only if VIO>VIO_UV AND if VBAT OR VCC is within the functional range, then SPI communication between the

microcontroller and the transceiver can be established. The SPI uses four interface signals for synchronization

and data transfer:

• CSN: SPI chip select (active low)

•SCLK: SPI clock

• MOSI: SPI data input

• MISO: SPI data output

Figure 42 shows the SPI data transfer.

Figure 42

SPI Data Transfer

The SPI command transmission cycle begins when the transceiver is selected by the CSN pin (active low).

When the signal of the CSN input pin returns from “low” to “high”, the TLE9255W decodes the data that was

shifted in on the MOSI. The data of MOSI and MISO is shifted in and out (MSB comes first) on every rising edge

of SCLK. The bit sampling is performed on every falling edge of SCLK. If the CSN input pin is “high”, then the

MISO pin has a high impedance. The SPI of the transceiver does not support TLE9255W daisy chaining.

The MISO pin signals invalid SPI commands (Chapter 8.5) or SPI failures (Chapter 8.4). If an invalid SPI

14 13 12 11 10 9

CSN high to low: MISO is enabled (low impedance).

Status information transferred to output shift register

CSN low to high: data from shift register is transferred to output functions

Data will be

shifted in

Actual status

Actual data

New data

New status

MISO

MOSI

CSN

SCLK

time

Min. CSN high-time to

be ensured

15 14 13 12 11 10 9

15 14

Data will be

shifted out

Bit sampling will

be performed

Bit sampling will

be performed

Err

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