EM78P568

8-bit OTP Micro-controller

__________________________________________________________________________________________________________________________________________________________________

* This specification are subject to be changed without notice.

29

01/31/2004

V4.7

Fig.11 The comparator timing

IOC6 (PORT6 I/O control, P6* pins switch control)

PAGE0 (PORT6 I/O control register)

7

6

5

4

3

2

1

0

IOC67

IOC66

IOC65

IOC64

IOC63

IOC62

IOC61

IOC60

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

Bit 0 ~ Bit 7 (IOC60 ~ IOC67) : PORT6(0~7) I/O direction control register

0

put the relative I/O pin as output

1

put the relative I/O pin into high impedance

PAGE1 (P6* pins switch control register)

7

6

5

4

3

2

1

0

AMUTE

P66S

P65S

P64S

P63S

P62S

-

-

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

Bit 0 ~ Bit 1 : (remain these values to “0” unchanged if PORT60,61 are used)

Bit 2(P62S) : Select channel 2 input pin of comparator or I/O PORT63 pin

0

P62 (I/O PORT62) pin is selected

1

CMP1 (Channel 1 input of comparator) pin is selected

Bit 3(P63S) : Select channel 2 input pin of comparator or I/O PORT63 pin

0

P63 (I/O PORT63) pin is selected

1

CMP2 (Channel 2 input of comparator) pin is selected

Bit 4(P64S) : Select channel 3 input pin of comparator or I/O PORT64 pin

0

P64 (I/O PORT64) pin is selected

1

CMP3 (Channel 3 input of comparator) pin is selected

Bit 5(P65S) : Select receiving audio output pin of CTCSS or I/O PORT65 pin

0

P65 (I/O PORT65) pin is selected

1

AURX (Receiving audio output pin of CTCSS) pin is selected

CMPEN

CMP1 to CMP3

reference

voltage

CPU clock

CMPFLAG

Setup time 10us

Compare start

Compare end